Struct esp32c2_hal::pac::spi2::misc::W
pub struct W(_);Expand description
Register MISC writer
Implementations§
§impl W
impl W
pub fn cs0_dis(&mut self) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 0>
pub fn cs0_dis(&mut self) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 0>
Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.
pub fn cs1_dis(&mut self) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 1>
pub fn cs1_dis(&mut self) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 1>
Bit 1 - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.
pub fn cs2_dis(&mut self) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 2>
pub fn cs2_dis(&mut self) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 2>
Bit 2 - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.
pub fn cs3_dis(&mut self) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 3>
pub fn cs3_dis(&mut self) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 3>
Bit 3 - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.
pub fn cs4_dis(&mut self) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 4>
pub fn cs4_dis(&mut self) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 4>
Bit 4 - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.
pub fn cs5_dis(&mut self) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 5>
pub fn cs5_dis(&mut self) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 5>
Bit 5 - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.
pub fn ck_dis(&mut self) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 6>
pub fn ck_dis(&mut self) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 6>
Bit 6 - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.
pub fn master_cs_pol(
&mut self
) -> FieldWriterRaw<'_, u32, MISC_SPEC, u8, u8, Unsafe, 6, 7>
pub fn master_cs_pol(
&mut self
) -> FieldWriterRaw<'_, u32, MISC_SPEC, u8, u8, Unsafe, 6, 7>
Bits 7:12 - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
pub fn slave_cs_pol(
&mut self
) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 23>
pub fn slave_cs_pol(
&mut self
) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 23>
Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.
pub fn ck_idle_edge(
&mut self
) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 29>
pub fn ck_idle_edge(
&mut self
) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 29>
Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.
pub fn cs_keep_active(
&mut self
) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 30>
pub fn cs_keep_active(
&mut self
) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 30>
Bit 30 - spi cs line keep low when the bit is set. Can be configured in CONF state.
pub fn quad_din_pin_swap(
&mut self
) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 31>
pub fn quad_din_pin_swap(
&mut self
) -> BitWriterRaw<'_, u32, MISC_SPEC, bool, BitM, 31>
Bit 31 - 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state.
Methods from Deref<Target = W<MISC_SPEC>>§
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.
Safety
Read datasheet or reference manual to find what values are allowed to pass.