Struct esp32c2_hal::pac::spi2::clock::W
pub struct W(_);
Expand description
Register CLOCK
writer
Implementations§
§impl W
impl W
pub fn clkcnt_l(
&mut self
) -> FieldWriterRaw<'_, u32, CLOCK_SPEC, u8, u8, Unsafe, 6, 0>
pub fn clkcnt_l(
&mut self
) -> FieldWriterRaw<'_, u32, CLOCK_SPEC, u8, u8, Unsafe, 6, 0>
Bits 0:5 - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.
pub fn clkcnt_h(
&mut self
) -> FieldWriterRaw<'_, u32, CLOCK_SPEC, u8, u8, Unsafe, 6, 6>
pub fn clkcnt_h(
&mut self
) -> FieldWriterRaw<'_, u32, CLOCK_SPEC, u8, u8, Unsafe, 6, 6>
Bits 6:11 - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.
pub fn clkcnt_n(
&mut self
) -> FieldWriterRaw<'_, u32, CLOCK_SPEC, u8, u8, Unsafe, 6, 12>
pub fn clkcnt_n(
&mut self
) -> FieldWriterRaw<'_, u32, CLOCK_SPEC, u8, u8, Unsafe, 6, 12>
Bits 12:17 - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
pub fn clkdiv_pre(
&mut self
) -> FieldWriterRaw<'_, u32, CLOCK_SPEC, u8, u8, Unsafe, 4, 18>
pub fn clkdiv_pre(
&mut self
) -> FieldWriterRaw<'_, u32, CLOCK_SPEC, u8, u8, Unsafe, 4, 18>
Bits 18:21 - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.
pub fn clk_equ_sysclk(
&mut self
) -> BitWriterRaw<'_, u32, CLOCK_SPEC, bool, BitM, 31>
pub fn clk_equ_sysclk(
&mut self
) -> BitWriterRaw<'_, u32, CLOCK_SPEC, bool, BitM, 31>
Bit 31 - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.
Methods from Deref<Target = W<CLOCK_SPEC>>§
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.
Safety
Read datasheet or reference manual to find what values are allowed to pass.