Module esp32c2_hal::pac::spi0::ctrl2

SPI0 control2 register.

Structs

CTRL2_SPEC

SPI0 control2 register.

R

Register CTRL2 reader

W

Register CTRL2 writer

Type Definitions

CS_HOLD_DELAY_R

Field CS_HOLD_DELAY reader - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.

CS_HOLD_DELAY_W

Field CS_HOLD_DELAY writer - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.

CS_HOLD_TIME_R

Field CS_HOLD_TIME reader - Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.

CS_HOLD_TIME_W

Field CS_HOLD_TIME writer - Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.

CS_SETUP_TIME_R

Field CS_SETUP_TIME reader - (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.

CS_SETUP_TIME_W

Field CS_SETUP_TIME writer - (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.

SYNC_RESET_W

Field SYNC_RESET writer - The FSM will be reset.