Expand description

SPI1 bit mode control register.

Structs

SPI1 bit mode control register.
Register CACHE_FCTRL reader
Register CACHE_FCTRL writer

Type Definitions

Field CACHE_USR_ADDR_4BYTE reader - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
Field CACHE_USR_ADDR_4BYTE writer - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
Field FADDR_DUAL reader - For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
Field FADDR_DUAL writer - For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
Field FADDR_QUAD reader - For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
Field FADDR_QUAD writer - For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
Field FDIN_DUAL reader - For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
Field FDIN_DUAL writer - For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
Field FDIN_QUAD reader - For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
Field FDIN_QUAD writer - For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
Field FDOUT_DUAL reader - For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
Field FDOUT_DUAL writer - For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
Field FDOUT_QUAD reader - For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
Field FDOUT_QUAD writer - For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.