Struct esp32c2_hal::pac::uart0::int_ena::W

pub struct W(_);

Register INT_ENA writer

Implementations

impl W

pub fn rxfifo_full_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 0>

Bit 0 - This is the enable bit for rxfifo_full_int_st register.

pub fn txfifo_empty_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 1>

Bit 1 - This is the enable bit for txfifo_empty_int_st register.

pub fn parity_err_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 2>

Bit 2 - This is the enable bit for parity_err_int_st register.

pub fn frm_err_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 3>

Bit 3 - This is the enable bit for frm_err_int_st register.

pub fn rxfifo_ovf_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 4>

Bit 4 - This is the enable bit for rxfifo_ovf_int_st register.

pub fn dsr_chg_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 5>

Bit 5 - This is the enable bit for dsr_chg_int_st register.

pub fn cts_chg_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 6>

Bit 6 - This is the enable bit for cts_chg_int_st register.

pub fn brk_det_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 7>

Bit 7 - This is the enable bit for brk_det_int_st register.

pub fn rxfifo_tout_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 8>

Bit 8 - This is the enable bit for rxfifo_tout_int_st register.

pub fn sw_xon_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 9>

Bit 9 - This is the enable bit for sw_xon_int_st register.

pub fn sw_xoff_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 10>

Bit 10 - This is the enable bit for sw_xoff_int_st register.

pub fn glitch_det_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 11>

Bit 11 - This is the enable bit for glitch_det_int_st register.

pub fn tx_brk_done_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 12>

Bit 12 - This is the enable bit for tx_brk_done_int_st register.

pub fn tx_brk_idle_done_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 13>

Bit 13 - This is the enable bit for tx_brk_idle_done_int_st register.

pub fn tx_done_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 14>

Bit 14 - This is the enable bit for tx_done_int_st register.

pub fn rs485_parity_err_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 15>

Bit 15 - This is the enable bit for rs485_parity_err_int_st register.

pub fn rs485_frm_err_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 16>

Bit 16 - This is the enable bit for rs485_parity_err_int_st register.

pub fn rs485_clash_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 17>

Bit 17 - This is the enable bit for rs485_clash_int_st register.

pub fn at_cmd_char_det_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 18>

Bit 18 - This is the enable bit for at_cmd_char_det_int_st register.

pub fn wakeup_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 19>

Bit 19 - This is the enable bit for uart_wakeup_int_st register.

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<INT_ENA_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<INT_ENA_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<INT_ENA_SPEC>> for W

fn from(writer: W<INT_ENA_SPEC>) -> W

Converts to this type from the input type.