Struct esp32c2_hal::pac::uart0::conf0::R

pub struct R(_);
Expand description

Register CONF0 reader

Implementations

Bit 0 - This register is used to configure the parity check mode.

Bit 1 - Set this bit to enable uart parity check.

Bits 2:3 - This register is used to set the length of data.

Bits 4:5 - This register is used to set the length of stop bit.

Bit 6 - This register is used to configure the software rts signal which is used in software flow control.

Bit 7 - This register is used to configure the software dtr signal which is used in software flow control.

Bit 8 - Set this bit to enbale transmitter to send NULL when the process of sending data is done.

Bit 9 - Set this bit to enable IrDA loopback mode.

Bit 10 - This is the start enable bit for IrDA transmitter.

Bit 11 - 1’h1: The IrDA transmitter’s 11th bit is the same as 10th bit. 1’h0: Set IrDA transmitter’s 11th bit to 0.

Bit 12 - Set this bit to invert the level of IrDA transmitter.

Bit 13 - Set this bit to invert the level of IrDA receiver.

Bit 14 - Set this bit to enable uart loopback test mode.

Bit 15 - Set this bit to enable flow control function for transmitter.

Bit 16 - Set this bit to enable IrDA protocol.

Bit 17 - Set this bit to reset the uart receive-FIFO.

Bit 18 - Set this bit to reset the uart transmit-FIFO.

Bit 19 - Set this bit to inverse the level value of uart rxd signal.

Bit 20 - Set this bit to inverse the level value of uart cts signal.

Bit 21 - Set this bit to inverse the level value of uart dsr signal.

Bit 22 - Set this bit to inverse the level value of uart txd signal.

Bit 23 - Set this bit to inverse the level value of uart rts signal.

Bit 24 - Set this bit to inverse the level value of uart dtr signal.

Bit 25 - 1’h1: Force clock on for register. 1’h0: Support clock only when application writes registers.

Bit 26 - 1’h1: Receiver stops storing data into FIFO when data is wrong. 1’h0: Receiver stores the data even if the received data is wrong.

Bit 27 - This is the enable bit for detecting baudrate.

Bit 28 - UART memory clock gate enable signal.

Methods from Deref<Target = R<CONF0_SPEC>>

Reads raw bits from register.

Trait Implementations

The resulting type after dereferencing.
Dereferences the value.
Converts to this type from the input type.

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Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

The type returned in the event of a conversion error.
Performs the conversion.
The type returned in the event of a conversion error.
Performs the conversion.