Struct esp32c2_hal::pac::spi2::dout_mode::R

pub struct R(_);

Register DOUT_MODE reader

Implementations

impl R

pub fn dout0_mode(&self) -> BitReaderRaw<bool>

Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn dout1_mode(&self) -> BitReaderRaw<bool>

Bit 1 - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn dout2_mode(&self) -> BitReaderRaw<bool>

Bit 2 - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn dout3_mode(&self) -> BitReaderRaw<bool>

Bit 3 - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn dout4_mode(&self) -> BitReaderRaw<bool>

Bit 4 - The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn dout5_mode(&self) -> BitReaderRaw<bool>

Bit 5 - The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn dout6_mode(&self) -> BitReaderRaw<bool>

Bit 6 - The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn dout7_mode(&self) -> BitReaderRaw<bool>

Bit 7 - The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn d_dqs_mode(&self) -> BitReaderRaw<bool>

Bit 8 - The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

Methods from Deref<Target = R<DOUT_MODE_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<DOUT_MODE_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<DOUT_MODE_SPEC>> for R

fn from(reader: R<DOUT_MODE_SPEC>) -> R

Converts to this type from the input type.