Struct esp32c2_hal::pac::spi2::din_num::R
pub struct R(_);
Expand description
Register DIN_NUM
reader
Implementations
impl R
impl R
pub fn din0_num(&self) -> FieldReaderRaw<u8, u8>
pub fn din0_num(&self) -> FieldReaderRaw<u8, u8>
Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.
pub fn din1_num(&self) -> FieldReaderRaw<u8, u8>
pub fn din1_num(&self) -> FieldReaderRaw<u8, u8>
Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.
pub fn din2_num(&self) -> FieldReaderRaw<u8, u8>
pub fn din2_num(&self) -> FieldReaderRaw<u8, u8>
Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.
pub fn din3_num(&self) -> FieldReaderRaw<u8, u8>
pub fn din3_num(&self) -> FieldReaderRaw<u8, u8>
Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.
pub fn din4_num(&self) -> FieldReaderRaw<u8, u8>
pub fn din4_num(&self) -> FieldReaderRaw<u8, u8>
Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.
pub fn din5_num(&self) -> FieldReaderRaw<u8, u8>
pub fn din5_num(&self) -> FieldReaderRaw<u8, u8>
Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.
Methods from Deref<Target = R<DIN_NUM_SPEC>>
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
Reads raw bits from register.