Struct esp32c2_hal::pac::spi1::cache_fctrl::W
pub struct W(_);
Expand description
Register CACHE_FCTRL
writer
Implementations
impl W
impl W
pub fn cache_usr_addr_4byte(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 1>
pub fn cache_usr_addr_4byte(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 1>
Bit 1 - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
pub fn fdin_dual(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 3>
pub fn fdin_dual(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 3>
Bit 3 - For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
pub fn fdout_dual(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 4>
pub fn fdout_dual(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 4>
Bit 4 - For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
pub fn faddr_dual(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 5>
pub fn faddr_dual(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 5>
Bit 5 - For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
pub fn fdin_quad(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 6>
pub fn fdin_quad(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 6>
Bit 6 - For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
pub fn fdout_quad(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 7>
pub fn fdout_quad(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 7>
Bit 7 - For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
pub fn faddr_quad(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 8>
pub fn faddr_quad(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 8>
Bit 8 - For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
Methods from Deref<Target = W<CACHE_FCTRL_SPEC>>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.
Safety
Read datasheet or reference manual to find what values are allowed to pass.