Struct esp32c2_hal::pac::spi1::cache_fctrl::R
pub struct R(_);
Expand description
Register CACHE_FCTRL
reader
Implementations
impl R
impl R
pub fn cache_usr_addr_4byte(&self) -> BitReaderRaw<bool>
pub fn cache_usr_addr_4byte(&self) -> BitReaderRaw<bool>
Bit 1 - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
pub fn fdin_dual(&self) -> BitReaderRaw<bool>
pub fn fdin_dual(&self) -> BitReaderRaw<bool>
Bit 3 - For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
pub fn fdout_dual(&self) -> BitReaderRaw<bool>
pub fn fdout_dual(&self) -> BitReaderRaw<bool>
Bit 4 - For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
pub fn faddr_dual(&self) -> BitReaderRaw<bool>
pub fn faddr_dual(&self) -> BitReaderRaw<bool>
Bit 5 - For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
pub fn fdin_quad(&self) -> BitReaderRaw<bool>
pub fn fdin_quad(&self) -> BitReaderRaw<bool>
Bit 6 - For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
pub fn fdout_quad(&self) -> BitReaderRaw<bool>
pub fn fdout_quad(&self) -> BitReaderRaw<bool>
Bit 7 - For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
pub fn faddr_quad(&self) -> BitReaderRaw<bool>
pub fn faddr_quad(&self) -> BitReaderRaw<bool>
Bit 8 - For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
Methods from Deref<Target = R<CACHE_FCTRL_SPEC>>
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
Reads raw bits from register.