Struct esp32c2_hal::pac::spi1::cache_fctrl::R

pub struct R(_);
Expand description

Register CACHE_FCTRL reader

Implementations

Bit 1 - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.

Bit 3 - For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.

Bit 4 - For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.

Bit 5 - For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.

Bit 6 - For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.

Bit 7 - For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.

Bit 8 - For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.

Methods from Deref<Target = R<CACHE_FCTRL_SPEC>>

Reads raw bits from register.

Trait Implementations

The resulting type after dereferencing.
Dereferences the value.
Converts to this type from the input type.

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Returns the argument unchanged.

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

The type returned in the event of a conversion error.
Performs the conversion.
The type returned in the event of a conversion error.
Performs the conversion.