Struct esp32c2_hal::pac::i2c0::fifo_conf::R

pub struct R(_);
Expand description

Register FIFO_CONF reader

Implementations

Bits 0:3 - The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid.

Bits 5:8 - The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid.

Bit 10 - Set this bit to enable APB nonfifo access.

Bit 12 - Set this bit to reset rx-fifo.

Bit 13 - Set this bit to reset tx-fifo.

Bit 14 - The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.

Methods from Deref<Target = R<FIFO_CONF_SPEC>>

Reads raw bits from register.

Trait Implementations

The resulting type after dereferencing.
Dereferences the value.
Converts to this type from the input type.

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