Struct esp32c2_hal::pac::extmem::cache_ilg_int_clr::W

pub struct W(_);

Register CACHE_ILG_INT_CLR writer

Implementations

impl W

pub fn icache_sync_op_fault_int_clr(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 0>

Bit 0 - The bit is used to clear interrupt by sync configurations fault.

pub fn icache_preload_op_fault_int_clr(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 1>

Bit 1 - The bit is used to clear interrupt by preload configurations fault.

pub fn mmu_entry_fault_int_clr(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 5>

Bit 5 - The bit is used to clear interrupt by mmu entry fault.

pub fn ibus_cnt_ovf_int_clr(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 7>

Bit 7 - The bit is used to clear interrupt by ibus counter overflow.

pub fn dbus_cnt_ovf_int_clr(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 8>

Bit 8 - The bit is used to clear interrupt by dbus counter overflow.

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<CACHE_ILG_INT_CLR_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CACHE_ILG_INT_CLR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<CACHE_ILG_INT_CLR_SPEC>> for W

fn from(writer: W<CACHE_ILG_INT_CLR_SPEC>) -> W

Converts to this type from the input type.