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#[doc = "Reader of register MEM_RX_STATUS"]
pub type R = crate::R<u32, super::MEM_RX_STATUS>;
#[doc = "Writer for register MEM_RX_STATUS"]
pub type W = crate::W<u32, super::MEM_RX_STATUS>;
#[doc = "Register MEM_RX_STATUS `reset()`'s with value 0"]
impl crate::ResetValue for super::MEM_RX_STATUS {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
#[doc = "Reader of field `MEM_RX_STATUS`"]
pub type MEM_RX_STATUS_R = crate::R<u32, u32>;
#[doc = "Write proxy for field `MEM_RX_STATUS`"]
pub struct MEM_RX_STATUS_W<'a> {
    w: &'a mut W,
}
impl<'a> MEM_RX_STATUS_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u32) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x00ff_ffff) | ((value as u32) & 0x00ff_ffff);
        self.w
    }
}
#[doc = "Reader of field `MEM_RX_RD_ADDR`"]
pub type MEM_RX_RD_ADDR_R = crate::R<u16, u16>;
#[doc = "Write proxy for field `MEM_RX_RD_ADDR`"]
pub struct MEM_RX_RD_ADDR_W<'a> {
    w: &'a mut W,
}
impl<'a> MEM_RX_RD_ADDR_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u16) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x07ff << 2)) | (((value as u32) & 0x07ff) << 2);
        self.w
    }
}
#[doc = "Reader of field `MEM_RX_WR_ADDR`"]
pub type MEM_RX_WR_ADDR_R = crate::R<u16, u16>;
#[doc = "Write proxy for field `MEM_RX_WR_ADDR`"]
pub struct MEM_RX_WR_ADDR_W<'a> {
    w: &'a mut W,
}
impl<'a> MEM_RX_WR_ADDR_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u16) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x07ff << 13)) | (((value as u32) & 0x07ff) << 13);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:23"]
    #[inline(always)]
    pub fn mem_rx_status(&self) -> MEM_RX_STATUS_R {
        MEM_RX_STATUS_R::new((self.bits & 0x00ff_ffff) as u32)
    }
    #[doc = "Bits 2:12"]
    #[inline(always)]
    pub fn mem_rx_rd_addr(&self) -> MEM_RX_RD_ADDR_R {
        MEM_RX_RD_ADDR_R::new(((self.bits >> 2) & 0x07ff) as u16)
    }
    #[doc = "Bits 13:23"]
    #[inline(always)]
    pub fn mem_rx_wr_addr(&self) -> MEM_RX_WR_ADDR_R {
        MEM_RX_WR_ADDR_R::new(((self.bits >> 13) & 0x07ff) as u16)
    }
}
impl W {
    #[doc = "Bits 0:23"]
    #[inline(always)]
    pub fn mem_rx_status(&mut self) -> MEM_RX_STATUS_W {
        MEM_RX_STATUS_W { w: self }
    }
    #[doc = "Bits 2:12"]
    #[inline(always)]
    pub fn mem_rx_rd_addr(&mut self) -> MEM_RX_RD_ADDR_W {
        MEM_RX_RD_ADDR_W { w: self }
    }
    #[doc = "Bits 13:23"]
    #[inline(always)]
    pub fn mem_rx_wr_addr(&mut self) -> MEM_RX_WR_ADDR_W {
        MEM_RX_WR_ADDR_W { w: self }
    }
}