1#[doc = "Register `INT_ST` reader"]
2pub type R = crate::R<INT_ST_SPEC>;
3#[doc = "Field `RXFIFO_FULL` reader - The masked interrupt status for rxfifo_full_int interrupt."]
4pub type RXFIFO_FULL_R = crate::BitReader;
5#[doc = "Field `TXFIFO_EMPTY` reader - The masked interrupt status for txfifo_empty_int interrupt."]
6pub type TXFIFO_EMPTY_R = crate::BitReader;
7#[doc = "Field `RXFIFO_OVF` reader - The masked interrupt status for rxfifo_ovf_int interrupt."]
8pub type RXFIFO_OVF_R = crate::BitReader;
9#[doc = "Field `END_DETECT` reader - The masked interrupt status for end_detect_int interrupt."]
10pub type END_DETECT_R = crate::BitReader;
11#[doc = "Field `SLAVE_TRAN_COMP` reader - The masked interrupt status for slave_tran_comp_int interrupt."]
12pub type SLAVE_TRAN_COMP_R = crate::BitReader;
13#[doc = "Field `ARBITRATION_LOST` reader - The masked interrupt status for arbitration_lost_int interrupt."]
14pub type ARBITRATION_LOST_R = crate::BitReader;
15#[doc = "Field `MASTER_TRAN_COMP` reader - The masked interrupt status for master_tran_comp_int interrupt."]
16pub type MASTER_TRAN_COMP_R = crate::BitReader;
17#[doc = "Field `TRANS_COMPLETE` reader - The masked interrupt status for trans_complete_int interrupt."]
18pub type TRANS_COMPLETE_R = crate::BitReader;
19#[doc = "Field `TIME_OUT` reader - The masked interrupt status for time_out_int interrupt."]
20pub type TIME_OUT_R = crate::BitReader;
21#[doc = "Field `TRANS_START` reader - The masked interrupt status for trans_start_int interrupt."]
22pub type TRANS_START_R = crate::BitReader;
23#[doc = "Field `NACK` reader - The masked interrupt status for ack_err_int interrupt."]
24pub type NACK_R = crate::BitReader;
25#[doc = "Field `RX_REC_FULL` reader - The masked interrupt status for rx_rec_full_int interrupt."]
26pub type RX_REC_FULL_R = crate::BitReader;
27#[doc = "Field `TX_SEND_EMPTY` reader - The masked interrupt status for tx_send_empty_int interrupt."]
28pub type TX_SEND_EMPTY_R = crate::BitReader;
29impl R {
30 #[doc = "Bit 0 - The masked interrupt status for rxfifo_full_int interrupt."]
31 #[inline(always)]
32 pub fn rxfifo_full(&self) -> RXFIFO_FULL_R {
33 RXFIFO_FULL_R::new((self.bits & 1) != 0)
34 }
35 #[doc = "Bit 1 - The masked interrupt status for txfifo_empty_int interrupt."]
36 #[inline(always)]
37 pub fn txfifo_empty(&self) -> TXFIFO_EMPTY_R {
38 TXFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0)
39 }
40 #[doc = "Bit 2 - The masked interrupt status for rxfifo_ovf_int interrupt."]
41 #[inline(always)]
42 pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R {
43 RXFIFO_OVF_R::new(((self.bits >> 2) & 1) != 0)
44 }
45 #[doc = "Bit 3 - The masked interrupt status for end_detect_int interrupt."]
46 #[inline(always)]
47 pub fn end_detect(&self) -> END_DETECT_R {
48 END_DETECT_R::new(((self.bits >> 3) & 1) != 0)
49 }
50 #[doc = "Bit 4 - The masked interrupt status for slave_tran_comp_int interrupt."]
51 #[inline(always)]
52 pub fn slave_tran_comp(&self) -> SLAVE_TRAN_COMP_R {
53 SLAVE_TRAN_COMP_R::new(((self.bits >> 4) & 1) != 0)
54 }
55 #[doc = "Bit 5 - The masked interrupt status for arbitration_lost_int interrupt."]
56 #[inline(always)]
57 pub fn arbitration_lost(&self) -> ARBITRATION_LOST_R {
58 ARBITRATION_LOST_R::new(((self.bits >> 5) & 1) != 0)
59 }
60 #[doc = "Bit 6 - The masked interrupt status for master_tran_comp_int interrupt."]
61 #[inline(always)]
62 pub fn master_tran_comp(&self) -> MASTER_TRAN_COMP_R {
63 MASTER_TRAN_COMP_R::new(((self.bits >> 6) & 1) != 0)
64 }
65 #[doc = "Bit 7 - The masked interrupt status for trans_complete_int interrupt."]
66 #[inline(always)]
67 pub fn trans_complete(&self) -> TRANS_COMPLETE_R {
68 TRANS_COMPLETE_R::new(((self.bits >> 7) & 1) != 0)
69 }
70 #[doc = "Bit 8 - The masked interrupt status for time_out_int interrupt."]
71 #[inline(always)]
72 pub fn time_out(&self) -> TIME_OUT_R {
73 TIME_OUT_R::new(((self.bits >> 8) & 1) != 0)
74 }
75 #[doc = "Bit 9 - The masked interrupt status for trans_start_int interrupt."]
76 #[inline(always)]
77 pub fn trans_start(&self) -> TRANS_START_R {
78 TRANS_START_R::new(((self.bits >> 9) & 1) != 0)
79 }
80 #[doc = "Bit 10 - The masked interrupt status for ack_err_int interrupt."]
81 #[inline(always)]
82 pub fn nack(&self) -> NACK_R {
83 NACK_R::new(((self.bits >> 10) & 1) != 0)
84 }
85 #[doc = "Bit 11 - The masked interrupt status for rx_rec_full_int interrupt."]
86 #[inline(always)]
87 pub fn rx_rec_full(&self) -> RX_REC_FULL_R {
88 RX_REC_FULL_R::new(((self.bits >> 11) & 1) != 0)
89 }
90 #[doc = "Bit 12 - The masked interrupt status for tx_send_empty_int interrupt."]
91 #[inline(always)]
92 pub fn tx_send_empty(&self) -> TX_SEND_EMPTY_R {
93 TX_SEND_EMPTY_R::new(((self.bits >> 12) & 1) != 0)
94 }
95}
96#[cfg(feature = "impl-register-debug")]
97impl core::fmt::Debug for R {
98 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
99 f.debug_struct("INT_ST")
100 .field("rxfifo_full", &self.rxfifo_full())
101 .field("txfifo_empty", &self.txfifo_empty())
102 .field("rxfifo_ovf", &self.rxfifo_ovf())
103 .field("end_detect", &self.end_detect())
104 .field("slave_tran_comp", &self.slave_tran_comp())
105 .field("arbitration_lost", &self.arbitration_lost())
106 .field("master_tran_comp", &self.master_tran_comp())
107 .field("trans_complete", &self.trans_complete())
108 .field("time_out", &self.time_out())
109 .field("trans_start", &self.trans_start())
110 .field("nack", &self.nack())
111 .field("rx_rec_full", &self.rx_rec_full())
112 .field("tx_send_empty", &self.tx_send_empty())
113 .finish()
114 }
115}
116#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
117pub struct INT_ST_SPEC;
118impl crate::RegisterSpec for INT_ST_SPEC {
119 type Ux = u32;
120}
121#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
122impl crate::Readable for INT_ST_SPEC {}
123#[doc = "`reset()` method sets INT_ST to value 0"]
124impl crate::Resettable for INT_ST_SPEC {}