Type Alias R

pub type R = R<CHCONF1_SPEC>;

Register CH%sCONF1 reader

Aliased Type

pub struct R { /* private fields */ }

Implementations

impl R

pub fn tx_start(&self) -> TX_START_R

Bit 0 - Set this bit to start sending data for channel0.

pub fn rx_en(&self) -> RX_EN_R

Bit 1 - Set this bit to enbale receving data for channel0.

pub fn mem_wr_rst(&self) -> MEM_WR_RST_R

Bit 2 - Set this bit to reset write ram address for channel0 by receiver access.

pub fn mem_rd_rst(&self) -> MEM_RD_RST_R

Bit 3 - Set this bit to reset read ram address for channel0 by transmitter access.

pub fn apb_mem_rst(&self) -> APB_MEM_RST_R

Bit 4 - Set this bit to reset W/R ram address for channel0 by apb fifo access

pub fn mem_owner(&self) -> MEM_OWNER_R

Bit 5 - This is the mark of channel0’s ram usage right.1’b1：receiver uses the ram 0：transmitter uses the ram

pub fn tx_conti_mode(&self) -> TX_CONTI_MODE_R

Bit 6 - Set this bit to continue sending from the first data to the last data in channel0 again and again.

pub fn rx_filter_en(&self) -> RX_FILTER_EN_R

Bit 7 - This is the receive filter enable bit for channel0.

pub fn rx_filter_thres(&self) -> RX_FILTER_THRES_R

Bits 8:15 - in receive mode channel0 ignore input pulse when the pulse width is smaller then this value.

pub fn ref_cnt_rst(&self) -> REF_CNT_RST_R

Bit 16 - This bit is used to reset divider in channel0.

pub fn ref_always_on(&self) -> REF_ALWAYS_ON_R

Bit 17 - This bit is used to select base clock. 1’b1:clk_apb 1’b0:clk_ref

pub fn idle_out_lv(&self) -> IDLE_OUT_LV_R

Bit 18 - This bit configures the output signal’s level for channel0 in IDLE state.

pub fn idle_out_en(&self) -> IDLE_OUT_EN_R

Bit 19 - This is the output enable control bit for channel0 in IDLE state.