esp32/
emac_ext.rs

1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5    ex_clkout_conf: EX_CLKOUT_CONF,
6    ex_oscclk_conf: EX_OSCCLK_CONF,
7    ex_clk_ctrl: EX_CLK_CTRL,
8    ex_phyinf_conf: EX_PHYINF_CONF,
9    pd_sel: PD_SEL,
10    _reserved5: [u8; 0xe8],
11    ex_date: EX_DATE,
12}
13impl RegisterBlock {
14    #[doc = "0x00 - RMII clock divider setting"]
15    #[inline(always)]
16    pub const fn ex_clkout_conf(&self) -> &EX_CLKOUT_CONF {
17        &self.ex_clkout_conf
18    }
19    #[doc = "0x04 - RMII clock half and whole divider settings"]
20    #[inline(always)]
21    pub const fn ex_oscclk_conf(&self) -> &EX_OSCCLK_CONF {
22        &self.ex_oscclk_conf
23    }
24    #[doc = "0x08 - Clock enable and external/internal clock selection"]
25    #[inline(always)]
26    pub const fn ex_clk_ctrl(&self) -> &EX_CLK_CTRL {
27        &self.ex_clk_ctrl
28    }
29    #[doc = "0x0c - Selection of MII/RMII phy"]
30    #[inline(always)]
31    pub const fn ex_phyinf_conf(&self) -> &EX_PHYINF_CONF {
32        &self.ex_phyinf_conf
33    }
34    #[doc = "0x10 - Ethernet RAM power-down enable"]
35    #[inline(always)]
36    pub const fn pd_sel(&self) -> &PD_SEL {
37        &self.pd_sel
38    }
39    #[doc = "0xfc - "]
40    #[inline(always)]
41    pub const fn ex_date(&self) -> &EX_DATE {
42        &self.ex_date
43    }
44}
45#[doc = "EX_CLKOUT_CONF (rw) register accessor: RMII clock divider setting\n\nYou can [`read`](crate::Reg::read) this register and get [`ex_clkout_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ex_clkout_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ex_clkout_conf`] module"]
46pub type EX_CLKOUT_CONF = crate::Reg<ex_clkout_conf::EX_CLKOUT_CONF_SPEC>;
47#[doc = "RMII clock divider setting"]
48pub mod ex_clkout_conf;
49#[doc = "EX_OSCCLK_CONF (rw) register accessor: RMII clock half and whole divider settings\n\nYou can [`read`](crate::Reg::read) this register and get [`ex_oscclk_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ex_oscclk_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ex_oscclk_conf`] module"]
50pub type EX_OSCCLK_CONF = crate::Reg<ex_oscclk_conf::EX_OSCCLK_CONF_SPEC>;
51#[doc = "RMII clock half and whole divider settings"]
52pub mod ex_oscclk_conf;
53#[doc = "EX_CLK_CTRL (rw) register accessor: Clock enable and external/internal clock selection\n\nYou can [`read`](crate::Reg::read) this register and get [`ex_clk_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ex_clk_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ex_clk_ctrl`] module"]
54pub type EX_CLK_CTRL = crate::Reg<ex_clk_ctrl::EX_CLK_CTRL_SPEC>;
55#[doc = "Clock enable and external/internal clock selection"]
56pub mod ex_clk_ctrl;
57#[doc = "EX_PHYINF_CONF (rw) register accessor: Selection of MII/RMII phy\n\nYou can [`read`](crate::Reg::read) this register and get [`ex_phyinf_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ex_phyinf_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ex_phyinf_conf`] module"]
58pub type EX_PHYINF_CONF = crate::Reg<ex_phyinf_conf::EX_PHYINF_CONF_SPEC>;
59#[doc = "Selection of MII/RMII phy"]
60pub mod ex_phyinf_conf;
61#[doc = "PD_SEL (rw) register accessor: Ethernet RAM power-down enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pd_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pd_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pd_sel`] module"]
62pub type PD_SEL = crate::Reg<pd_sel::PD_SEL_SPEC>;
63#[doc = "Ethernet RAM power-down enable"]
64pub mod pd_sel;
65#[doc = "EX_DATE (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`ex_date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ex_date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ex_date`] module"]
66pub type EX_DATE = crate::Reg<ex_date::EX_DATE_SPEC>;
67#[doc = ""]
68pub mod ex_date;
esp32/emac_ext.rs

esp32/
emac_ext.rs
