esp32/rtc_cntl/
slp_timer1.rs

1#[doc = "Register `SLP_TIMER1` reader"]
2pub type R = crate::R<SLP_TIMER1_SPEC>;
3#[doc = "Register `SLP_TIMER1` writer"]
4pub type W = crate::W<SLP_TIMER1_SPEC>;
5#[doc = "Field `SLP_VAL_HI` reader - RTC sleep timer high 16 bits"]
6pub type SLP_VAL_HI_R = crate::FieldReader<u16>;
7#[doc = "Field `SLP_VAL_HI` writer - RTC sleep timer high 16 bits"]
8pub type SLP_VAL_HI_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9#[doc = "Field `MAIN_TIMER_ALARM_EN` reader - timer alarm enable bit"]
10pub type MAIN_TIMER_ALARM_EN_R = crate::BitReader;
11#[doc = "Field `MAIN_TIMER_ALARM_EN` writer - timer alarm enable bit"]
12pub type MAIN_TIMER_ALARM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bits 0:15 - RTC sleep timer high 16 bits"]
15    #[inline(always)]
16    pub fn slp_val_hi(&self) -> SLP_VAL_HI_R {
17        SLP_VAL_HI_R::new((self.bits & 0xffff) as u16)
18    }
19    #[doc = "Bit 16 - timer alarm enable bit"]
20    #[inline(always)]
21    pub fn main_timer_alarm_en(&self) -> MAIN_TIMER_ALARM_EN_R {
22        MAIN_TIMER_ALARM_EN_R::new(((self.bits >> 16) & 1) != 0)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("SLP_TIMER1")
29            .field("slp_val_hi", &self.slp_val_hi())
30            .field("main_timer_alarm_en", &self.main_timer_alarm_en())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bits 0:15 - RTC sleep timer high 16 bits"]
36    #[inline(always)]
37    pub fn slp_val_hi(&mut self) -> SLP_VAL_HI_W<SLP_TIMER1_SPEC> {
38        SLP_VAL_HI_W::new(self, 0)
39    }
40    #[doc = "Bit 16 - timer alarm enable bit"]
41    #[inline(always)]
42    pub fn main_timer_alarm_en(&mut self) -> MAIN_TIMER_ALARM_EN_W<SLP_TIMER1_SPEC> {
43        MAIN_TIMER_ALARM_EN_W::new(self, 16)
44    }
45}
46#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`slp_timer1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slp_timer1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct SLP_TIMER1_SPEC;
48impl crate::RegisterSpec for SLP_TIMER1_SPEC {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [`slp_timer1::R`](R) reader structure"]
52impl crate::Readable for SLP_TIMER1_SPEC {}
53#[doc = "`write(|w| ..)` method takes [`slp_timer1::W`](W) writer structure"]
54impl crate::Writable for SLP_TIMER1_SPEC {
55    type Safety = crate::Unsafe;
56    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
57    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
58}
59#[doc = "`reset()` method sets SLP_TIMER1 to value 0"]
60impl crate::Resettable for SLP_TIMER1_SPEC {
61    const RESET_VALUE: u32 = 0;
62}
esp32/rtc_cntl/slp_timer1.rs

esp32/rtc_cntl/
slp_timer1.rs
