pub type R = R<CMD_SPEC>;
Expand description
Register CMD
reader
Aliased Type§
struct R { /* private fields */ }
Implementations§
Source§impl R
impl R
Sourcepub fn flash_per(&self) -> FLASH_PER_R
pub fn flash_per(&self) -> FLASH_PER_R
Bit 16 - program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
Sourcepub fn flash_pes(&self) -> FLASH_PES_R
pub fn flash_pes(&self) -> FLASH_PES_R
Bit 17 - program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
Sourcepub fn usr(&self) -> USR_R
pub fn usr(&self) -> USR_R
Bit 18 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
Sourcepub fn flash_hpm(&self) -> FLASH_HPM_R
pub fn flash_hpm(&self) -> FLASH_HPM_R
Bit 19 - Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.
Sourcepub fn flash_res(&self) -> FLASH_RES_R
pub fn flash_res(&self) -> FLASH_RES_R
Bit 20 - This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.
Sourcepub fn flash_dp(&self) -> FLASH_DP_R
pub fn flash_dp(&self) -> FLASH_DP_R
Bit 21 - Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
Sourcepub fn flash_ce(&self) -> FLASH_CE_R
pub fn flash_ce(&self) -> FLASH_CE_R
Bit 22 - Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
Sourcepub fn flash_be(&self) -> FLASH_BE_R
pub fn flash_be(&self) -> FLASH_BE_R
Bit 23 - Block erase enable. A 64KB block is erased via SPI command D8H. Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
Sourcepub fn flash_se(&self) -> FLASH_SE_R
pub fn flash_se(&self) -> FLASH_SE_R
Bit 24 - Sector erase enable. A 4KB sector is erased via SPI command 20H. Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
Sourcepub fn flash_pp(&self) -> FLASH_PP_R
pub fn flash_pp(&self) -> FLASH_PP_R
Bit 25 - Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.
Sourcepub fn flash_wrsr(&self) -> FLASH_WRSR_R
pub fn flash_wrsr(&self) -> FLASH_WRSR_R
Bit 26 - Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
Sourcepub fn flash_rdsr(&self) -> FLASH_RDSR_R
pub fn flash_rdsr(&self) -> FLASH_RDSR_R
Bit 27 - Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
Sourcepub fn flash_rdid(&self) -> FLASH_RDID_R
pub fn flash_rdid(&self) -> FLASH_RDID_R
Bit 28 - Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
Sourcepub fn flash_wrdi(&self) -> FLASH_WRDI_R
pub fn flash_wrdi(&self) -> FLASH_WRDI_R
Bit 29 - Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
Sourcepub fn flash_wren(&self) -> FLASH_WREN_R
pub fn flash_wren(&self) -> FLASH_WREN_R
Bit 30 - Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
Sourcepub fn flash_read(&self) -> FLASH_READ_R
pub fn flash_read(&self) -> FLASH_READ_R
Bit 31 - Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.