esp32/uhci0/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `RX_START` writer - "]
4pub type RX_START_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `TX_START` writer - "]
6pub type TX_START_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `RX_HUNG` writer - "]
8pub type RX_HUNG_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `TX_HUNG` writer - "]
10pub type TX_HUNG_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `IN_DONE` writer - "]
12pub type IN_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `IN_SUC_EOF` writer - "]
14pub type IN_SUC_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `IN_ERR_EOF` writer - "]
16pub type IN_ERR_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `OUT_DONE` writer - "]
18pub type OUT_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `OUT_EOF` writer - "]
20pub type OUT_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `IN_DSCR_ERR` writer - "]
22pub type IN_DSCR_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23#[doc = "Field `OUT_DSCR_ERR` writer - "]
24pub type OUT_DSCR_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `IN_DSCR_EMPTY` writer - "]
26pub type IN_DSCR_EMPTY_W<'a, REG> = crate::BitWriter1C<'a, REG>;
27#[doc = "Field `OUTLINK_EOF_ERR` writer - "]
28pub type OUTLINK_EOF_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `OUT_TOTAL_EOF` writer - "]
30pub type OUT_TOTAL_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
31#[doc = "Field `SEND_S_Q` writer - "]
32pub type SEND_S_Q_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `SEND_A_Q` writer - "]
34pub type SEND_A_Q_W<'a, REG> = crate::BitWriter1C<'a, REG>;
35#[doc = "Field `DMA_INFIFO_FULL_WM` writer - "]
36pub type DMA_INFIFO_FULL_WM_W<'a, REG> = crate::BitWriter1C<'a, REG>;
37#[cfg(feature = "impl-register-debug")]
38impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
39    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
40        write!(f, "(not readable)")
41    }
42}
43impl W {
44    #[doc = "Bit 0"]
45    #[inline(always)]
46    pub fn rx_start(&mut self) -> RX_START_W<INT_CLR_SPEC> {
47        RX_START_W::new(self, 0)
48    }
49    #[doc = "Bit 1"]
50    #[inline(always)]
51    pub fn tx_start(&mut self) -> TX_START_W<INT_CLR_SPEC> {
52        TX_START_W::new(self, 1)
53    }
54    #[doc = "Bit 2"]
55    #[inline(always)]
56    pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_CLR_SPEC> {
57        RX_HUNG_W::new(self, 2)
58    }
59    #[doc = "Bit 3"]
60    #[inline(always)]
61    pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_CLR_SPEC> {
62        TX_HUNG_W::new(self, 3)
63    }
64    #[doc = "Bit 4"]
65    #[inline(always)]
66    pub fn in_done(&mut self) -> IN_DONE_W<INT_CLR_SPEC> {
67        IN_DONE_W::new(self, 4)
68    }
69    #[doc = "Bit 5"]
70    #[inline(always)]
71    pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<INT_CLR_SPEC> {
72        IN_SUC_EOF_W::new(self, 5)
73    }
74    #[doc = "Bit 6"]
75    #[inline(always)]
76    pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<INT_CLR_SPEC> {
77        IN_ERR_EOF_W::new(self, 6)
78    }
79    #[doc = "Bit 7"]
80    #[inline(always)]
81    pub fn out_done(&mut self) -> OUT_DONE_W<INT_CLR_SPEC> {
82        OUT_DONE_W::new(self, 7)
83    }
84    #[doc = "Bit 8"]
85    #[inline(always)]
86    pub fn out_eof(&mut self) -> OUT_EOF_W<INT_CLR_SPEC> {
87        OUT_EOF_W::new(self, 8)
88    }
89    #[doc = "Bit 9"]
90    #[inline(always)]
91    pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<INT_CLR_SPEC> {
92        IN_DSCR_ERR_W::new(self, 9)
93    }
94    #[doc = "Bit 10"]
95    #[inline(always)]
96    pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<INT_CLR_SPEC> {
97        OUT_DSCR_ERR_W::new(self, 10)
98    }
99    #[doc = "Bit 11"]
100    #[inline(always)]
101    pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<INT_CLR_SPEC> {
102        IN_DSCR_EMPTY_W::new(self, 11)
103    }
104    #[doc = "Bit 12"]
105    #[inline(always)]
106    pub fn outlink_eof_err(&mut self) -> OUTLINK_EOF_ERR_W<INT_CLR_SPEC> {
107        OUTLINK_EOF_ERR_W::new(self, 12)
108    }
109    #[doc = "Bit 13"]
110    #[inline(always)]
111    pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<INT_CLR_SPEC> {
112        OUT_TOTAL_EOF_W::new(self, 13)
113    }
114    #[doc = "Bit 14"]
115    #[inline(always)]
116    pub fn send_s_q(&mut self) -> SEND_S_Q_W<INT_CLR_SPEC> {
117        SEND_S_Q_W::new(self, 14)
118    }
119    #[doc = "Bit 15"]
120    #[inline(always)]
121    pub fn send_a_q(&mut self) -> SEND_A_Q_W<INT_CLR_SPEC> {
122        SEND_A_Q_W::new(self, 15)
123    }
124    #[doc = "Bit 16"]
125    #[inline(always)]
126    pub fn dma_infifo_full_wm(&mut self) -> DMA_INFIFO_FULL_WM_W<INT_CLR_SPEC> {
127        DMA_INFIFO_FULL_WM_W::new(self, 16)
128    }
129}
130#[doc = "\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
131pub struct INT_CLR_SPEC;
132impl crate::RegisterSpec for INT_CLR_SPEC {
133    type Ux = u32;
134}
135#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
136impl crate::Writable for INT_CLR_SPEC {
137    type Safety = crate::Unsafe;
138    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
139    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0001_ffff;
140}
141#[doc = "`reset()` method sets INT_CLR to value 0"]
142impl crate::Resettable for INT_CLR_SPEC {
143    const RESET_VALUE: u32 = 0;
144}
esp32/uhci0/int_clr.rs

esp32/uhci0/
int_clr.rs
