esp32/slc/
_1rx_link.rs

1#[doc = "Register `_1RX_LINK` reader"]
2pub type R = crate::R<_1RX_LINK_SPEC>;
3#[doc = "Register `_1RX_LINK` writer"]
4pub type W = crate::W<_1RX_LINK_SPEC>;
5#[doc = "Field `SLC1_RXLINK_ADDR` reader - "]
6pub type SLC1_RXLINK_ADDR_R = crate::FieldReader<u32>;
7#[doc = "Field `SLC1_RXLINK_ADDR` writer - "]
8pub type SLC1_RXLINK_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
9#[doc = "Field `SLC1_BT_PACKET` reader - "]
10pub type SLC1_BT_PACKET_R = crate::BitReader;
11#[doc = "Field `SLC1_BT_PACKET` writer - "]
12pub type SLC1_BT_PACKET_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SLC1_RXLINK_STOP` reader - "]
14pub type SLC1_RXLINK_STOP_R = crate::BitReader;
15#[doc = "Field `SLC1_RXLINK_STOP` writer - "]
16pub type SLC1_RXLINK_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SLC1_RXLINK_START` reader - "]
18pub type SLC1_RXLINK_START_R = crate::BitReader;
19#[doc = "Field `SLC1_RXLINK_START` writer - "]
20pub type SLC1_RXLINK_START_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SLC1_RXLINK_RESTART` reader - "]
22pub type SLC1_RXLINK_RESTART_R = crate::BitReader;
23#[doc = "Field `SLC1_RXLINK_RESTART` writer - "]
24pub type SLC1_RXLINK_RESTART_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SLC1_RXLINK_PARK` reader - "]
26pub type SLC1_RXLINK_PARK_R = crate::BitReader;
27impl R {
28    #[doc = "Bits 0:19"]
29    #[inline(always)]
30    pub fn slc1_rxlink_addr(&self) -> SLC1_RXLINK_ADDR_R {
31        SLC1_RXLINK_ADDR_R::new(self.bits & 0x000f_ffff)
32    }
33    #[doc = "Bit 20"]
34    #[inline(always)]
35    pub fn slc1_bt_packet(&self) -> SLC1_BT_PACKET_R {
36        SLC1_BT_PACKET_R::new(((self.bits >> 20) & 1) != 0)
37    }
38    #[doc = "Bit 28"]
39    #[inline(always)]
40    pub fn slc1_rxlink_stop(&self) -> SLC1_RXLINK_STOP_R {
41        SLC1_RXLINK_STOP_R::new(((self.bits >> 28) & 1) != 0)
42    }
43    #[doc = "Bit 29"]
44    #[inline(always)]
45    pub fn slc1_rxlink_start(&self) -> SLC1_RXLINK_START_R {
46        SLC1_RXLINK_START_R::new(((self.bits >> 29) & 1) != 0)
47    }
48    #[doc = "Bit 30"]
49    #[inline(always)]
50    pub fn slc1_rxlink_restart(&self) -> SLC1_RXLINK_RESTART_R {
51        SLC1_RXLINK_RESTART_R::new(((self.bits >> 30) & 1) != 0)
52    }
53    #[doc = "Bit 31"]
54    #[inline(always)]
55    pub fn slc1_rxlink_park(&self) -> SLC1_RXLINK_PARK_R {
56        SLC1_RXLINK_PARK_R::new(((self.bits >> 31) & 1) != 0)
57    }
58}
59#[cfg(feature = "impl-register-debug")]
60impl core::fmt::Debug for R {
61    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
62        f.debug_struct("_1RX_LINK")
63            .field("slc1_rxlink_addr", &self.slc1_rxlink_addr())
64            .field("slc1_bt_packet", &self.slc1_bt_packet())
65            .field("slc1_rxlink_stop", &self.slc1_rxlink_stop())
66            .field("slc1_rxlink_start", &self.slc1_rxlink_start())
67            .field("slc1_rxlink_restart", &self.slc1_rxlink_restart())
68            .field("slc1_rxlink_park", &self.slc1_rxlink_park())
69            .finish()
70    }
71}
72impl W {
73    #[doc = "Bits 0:19"]
74    #[inline(always)]
75    pub fn slc1_rxlink_addr(&mut self) -> SLC1_RXLINK_ADDR_W<_1RX_LINK_SPEC> {
76        SLC1_RXLINK_ADDR_W::new(self, 0)
77    }
78    #[doc = "Bit 20"]
79    #[inline(always)]
80    pub fn slc1_bt_packet(&mut self) -> SLC1_BT_PACKET_W<_1RX_LINK_SPEC> {
81        SLC1_BT_PACKET_W::new(self, 20)
82    }
83    #[doc = "Bit 28"]
84    #[inline(always)]
85    pub fn slc1_rxlink_stop(&mut self) -> SLC1_RXLINK_STOP_W<_1RX_LINK_SPEC> {
86        SLC1_RXLINK_STOP_W::new(self, 28)
87    }
88    #[doc = "Bit 29"]
89    #[inline(always)]
90    pub fn slc1_rxlink_start(&mut self) -> SLC1_RXLINK_START_W<_1RX_LINK_SPEC> {
91        SLC1_RXLINK_START_W::new(self, 29)
92    }
93    #[doc = "Bit 30"]
94    #[inline(always)]
95    pub fn slc1_rxlink_restart(&mut self) -> SLC1_RXLINK_RESTART_W<_1RX_LINK_SPEC> {
96        SLC1_RXLINK_RESTART_W::new(self, 30)
97    }
98}
99#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`_1rx_link::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`_1rx_link::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
100pub struct _1RX_LINK_SPEC;
101impl crate::RegisterSpec for _1RX_LINK_SPEC {
102    type Ux = u32;
103}
104#[doc = "`read()` method returns [`_1rx_link::R`](R) reader structure"]
105impl crate::Readable for _1RX_LINK_SPEC {}
106#[doc = "`write(|w| ..)` method takes [`_1rx_link::W`](W) writer structure"]
107impl crate::Writable for _1RX_LINK_SPEC {
108    type Safety = crate::Unsafe;
109    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
110    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
111}
112#[doc = "`reset()` method sets _1RX_LINK to value 0x0010_0000"]
113impl crate::Resettable for _1RX_LINK_SPEC {
114    const RESET_VALUE: u32 = 0x0010_0000;
115}
esp32/slc/_1rx_link.rs

esp32/slc/
_1rx_link.rs
