1#[doc = "Register `_1INT_ST` reader"]
2pub type R = crate::R<_1INT_ST_SPEC>;
3#[doc = "Field `FRHOST_BIT8_INT_ST` reader - "]
4pub type FRHOST_BIT8_INT_ST_R = crate::BitReader;
5#[doc = "Field `FRHOST_BIT9_INT_ST` reader - "]
6pub type FRHOST_BIT9_INT_ST_R = crate::BitReader;
7#[doc = "Field `FRHOST_BIT10_INT_ST` reader - "]
8pub type FRHOST_BIT10_INT_ST_R = crate::BitReader;
9#[doc = "Field `FRHOST_BIT11_INT_ST` reader - "]
10pub type FRHOST_BIT11_INT_ST_R = crate::BitReader;
11#[doc = "Field `FRHOST_BIT12_INT_ST` reader - "]
12pub type FRHOST_BIT12_INT_ST_R = crate::BitReader;
13#[doc = "Field `FRHOST_BIT13_INT_ST` reader - "]
14pub type FRHOST_BIT13_INT_ST_R = crate::BitReader;
15#[doc = "Field `FRHOST_BIT14_INT_ST` reader - "]
16pub type FRHOST_BIT14_INT_ST_R = crate::BitReader;
17#[doc = "Field `FRHOST_BIT15_INT_ST` reader - "]
18pub type FRHOST_BIT15_INT_ST_R = crate::BitReader;
19#[doc = "Field `SLC1_RX_START_INT_ST` reader - "]
20pub type SLC1_RX_START_INT_ST_R = crate::BitReader;
21#[doc = "Field `SLC1_TX_START_INT_ST` reader - "]
22pub type SLC1_TX_START_INT_ST_R = crate::BitReader;
23#[doc = "Field `SLC1_RX_UDF_INT_ST` reader - "]
24pub type SLC1_RX_UDF_INT_ST_R = crate::BitReader;
25#[doc = "Field `SLC1_TX_OVF_INT_ST` reader - "]
26pub type SLC1_TX_OVF_INT_ST_R = crate::BitReader;
27#[doc = "Field `SLC1_TOKEN0_1TO0_INT_ST` reader - "]
28pub type SLC1_TOKEN0_1TO0_INT_ST_R = crate::BitReader;
29#[doc = "Field `SLC1_TOKEN1_1TO0_INT_ST` reader - "]
30pub type SLC1_TOKEN1_1TO0_INT_ST_R = crate::BitReader;
31#[doc = "Field `SLC1_TX_DONE_INT_ST` reader - "]
32pub type SLC1_TX_DONE_INT_ST_R = crate::BitReader;
33#[doc = "Field `SLC1_TX_SUC_EOF_INT_ST` reader - "]
34pub type SLC1_TX_SUC_EOF_INT_ST_R = crate::BitReader;
35#[doc = "Field `SLC1_RX_DONE_INT_ST` reader - "]
36pub type SLC1_RX_DONE_INT_ST_R = crate::BitReader;
37#[doc = "Field `SLC1_RX_EOF_INT_ST` reader - "]
38pub type SLC1_RX_EOF_INT_ST_R = crate::BitReader;
39#[doc = "Field `SLC1_TOHOST_INT_ST` reader - "]
40pub type SLC1_TOHOST_INT_ST_R = crate::BitReader;
41#[doc = "Field `SLC1_TX_DSCR_ERR_INT_ST` reader - "]
42pub type SLC1_TX_DSCR_ERR_INT_ST_R = crate::BitReader;
43#[doc = "Field `SLC1_RX_DSCR_ERR_INT_ST` reader - "]
44pub type SLC1_RX_DSCR_ERR_INT_ST_R = crate::BitReader;
45#[doc = "Field `SLC1_TX_DSCR_EMPTY_INT_ST` reader - "]
46pub type SLC1_TX_DSCR_EMPTY_INT_ST_R = crate::BitReader;
47#[doc = "Field `SLC1_HOST_RD_ACK_INT_ST` reader - "]
48pub type SLC1_HOST_RD_ACK_INT_ST_R = crate::BitReader;
49#[doc = "Field `SLC1_WR_RETRY_DONE_INT_ST` reader - "]
50pub type SLC1_WR_RETRY_DONE_INT_ST_R = crate::BitReader;
51#[doc = "Field `SLC1_TX_ERR_EOF_INT_ST` reader - "]
52pub type SLC1_TX_ERR_EOF_INT_ST_R = crate::BitReader;
53impl R {
54 #[doc = "Bit 0"]
55 #[inline(always)]
56 pub fn frhost_bit8_int_st(&self) -> FRHOST_BIT8_INT_ST_R {
57 FRHOST_BIT8_INT_ST_R::new((self.bits & 1) != 0)
58 }
59 #[doc = "Bit 1"]
60 #[inline(always)]
61 pub fn frhost_bit9_int_st(&self) -> FRHOST_BIT9_INT_ST_R {
62 FRHOST_BIT9_INT_ST_R::new(((self.bits >> 1) & 1) != 0)
63 }
64 #[doc = "Bit 2"]
65 #[inline(always)]
66 pub fn frhost_bit10_int_st(&self) -> FRHOST_BIT10_INT_ST_R {
67 FRHOST_BIT10_INT_ST_R::new(((self.bits >> 2) & 1) != 0)
68 }
69 #[doc = "Bit 3"]
70 #[inline(always)]
71 pub fn frhost_bit11_int_st(&self) -> FRHOST_BIT11_INT_ST_R {
72 FRHOST_BIT11_INT_ST_R::new(((self.bits >> 3) & 1) != 0)
73 }
74 #[doc = "Bit 4"]
75 #[inline(always)]
76 pub fn frhost_bit12_int_st(&self) -> FRHOST_BIT12_INT_ST_R {
77 FRHOST_BIT12_INT_ST_R::new(((self.bits >> 4) & 1) != 0)
78 }
79 #[doc = "Bit 5"]
80 #[inline(always)]
81 pub fn frhost_bit13_int_st(&self) -> FRHOST_BIT13_INT_ST_R {
82 FRHOST_BIT13_INT_ST_R::new(((self.bits >> 5) & 1) != 0)
83 }
84 #[doc = "Bit 6"]
85 #[inline(always)]
86 pub fn frhost_bit14_int_st(&self) -> FRHOST_BIT14_INT_ST_R {
87 FRHOST_BIT14_INT_ST_R::new(((self.bits >> 6) & 1) != 0)
88 }
89 #[doc = "Bit 7"]
90 #[inline(always)]
91 pub fn frhost_bit15_int_st(&self) -> FRHOST_BIT15_INT_ST_R {
92 FRHOST_BIT15_INT_ST_R::new(((self.bits >> 7) & 1) != 0)
93 }
94 #[doc = "Bit 8"]
95 #[inline(always)]
96 pub fn slc1_rx_start_int_st(&self) -> SLC1_RX_START_INT_ST_R {
97 SLC1_RX_START_INT_ST_R::new(((self.bits >> 8) & 1) != 0)
98 }
99 #[doc = "Bit 9"]
100 #[inline(always)]
101 pub fn slc1_tx_start_int_st(&self) -> SLC1_TX_START_INT_ST_R {
102 SLC1_TX_START_INT_ST_R::new(((self.bits >> 9) & 1) != 0)
103 }
104 #[doc = "Bit 10"]
105 #[inline(always)]
106 pub fn slc1_rx_udf_int_st(&self) -> SLC1_RX_UDF_INT_ST_R {
107 SLC1_RX_UDF_INT_ST_R::new(((self.bits >> 10) & 1) != 0)
108 }
109 #[doc = "Bit 11"]
110 #[inline(always)]
111 pub fn slc1_tx_ovf_int_st(&self) -> SLC1_TX_OVF_INT_ST_R {
112 SLC1_TX_OVF_INT_ST_R::new(((self.bits >> 11) & 1) != 0)
113 }
114 #[doc = "Bit 12"]
115 #[inline(always)]
116 pub fn slc1_token0_1to0_int_st(&self) -> SLC1_TOKEN0_1TO0_INT_ST_R {
117 SLC1_TOKEN0_1TO0_INT_ST_R::new(((self.bits >> 12) & 1) != 0)
118 }
119 #[doc = "Bit 13"]
120 #[inline(always)]
121 pub fn slc1_token1_1to0_int_st(&self) -> SLC1_TOKEN1_1TO0_INT_ST_R {
122 SLC1_TOKEN1_1TO0_INT_ST_R::new(((self.bits >> 13) & 1) != 0)
123 }
124 #[doc = "Bit 14"]
125 #[inline(always)]
126 pub fn slc1_tx_done_int_st(&self) -> SLC1_TX_DONE_INT_ST_R {
127 SLC1_TX_DONE_INT_ST_R::new(((self.bits >> 14) & 1) != 0)
128 }
129 #[doc = "Bit 15"]
130 #[inline(always)]
131 pub fn slc1_tx_suc_eof_int_st(&self) -> SLC1_TX_SUC_EOF_INT_ST_R {
132 SLC1_TX_SUC_EOF_INT_ST_R::new(((self.bits >> 15) & 1) != 0)
133 }
134 #[doc = "Bit 16"]
135 #[inline(always)]
136 pub fn slc1_rx_done_int_st(&self) -> SLC1_RX_DONE_INT_ST_R {
137 SLC1_RX_DONE_INT_ST_R::new(((self.bits >> 16) & 1) != 0)
138 }
139 #[doc = "Bit 17"]
140 #[inline(always)]
141 pub fn slc1_rx_eof_int_st(&self) -> SLC1_RX_EOF_INT_ST_R {
142 SLC1_RX_EOF_INT_ST_R::new(((self.bits >> 17) & 1) != 0)
143 }
144 #[doc = "Bit 18"]
145 #[inline(always)]
146 pub fn slc1_tohost_int_st(&self) -> SLC1_TOHOST_INT_ST_R {
147 SLC1_TOHOST_INT_ST_R::new(((self.bits >> 18) & 1) != 0)
148 }
149 #[doc = "Bit 19"]
150 #[inline(always)]
151 pub fn slc1_tx_dscr_err_int_st(&self) -> SLC1_TX_DSCR_ERR_INT_ST_R {
152 SLC1_TX_DSCR_ERR_INT_ST_R::new(((self.bits >> 19) & 1) != 0)
153 }
154 #[doc = "Bit 20"]
155 #[inline(always)]
156 pub fn slc1_rx_dscr_err_int_st(&self) -> SLC1_RX_DSCR_ERR_INT_ST_R {
157 SLC1_RX_DSCR_ERR_INT_ST_R::new(((self.bits >> 20) & 1) != 0)
158 }
159 #[doc = "Bit 21"]
160 #[inline(always)]
161 pub fn slc1_tx_dscr_empty_int_st(&self) -> SLC1_TX_DSCR_EMPTY_INT_ST_R {
162 SLC1_TX_DSCR_EMPTY_INT_ST_R::new(((self.bits >> 21) & 1) != 0)
163 }
164 #[doc = "Bit 22"]
165 #[inline(always)]
166 pub fn slc1_host_rd_ack_int_st(&self) -> SLC1_HOST_RD_ACK_INT_ST_R {
167 SLC1_HOST_RD_ACK_INT_ST_R::new(((self.bits >> 22) & 1) != 0)
168 }
169 #[doc = "Bit 23"]
170 #[inline(always)]
171 pub fn slc1_wr_retry_done_int_st(&self) -> SLC1_WR_RETRY_DONE_INT_ST_R {
172 SLC1_WR_RETRY_DONE_INT_ST_R::new(((self.bits >> 23) & 1) != 0)
173 }
174 #[doc = "Bit 24"]
175 #[inline(always)]
176 pub fn slc1_tx_err_eof_int_st(&self) -> SLC1_TX_ERR_EOF_INT_ST_R {
177 SLC1_TX_ERR_EOF_INT_ST_R::new(((self.bits >> 24) & 1) != 0)
178 }
179}
180#[cfg(feature = "impl-register-debug")]
181impl core::fmt::Debug for R {
182 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
183 f.debug_struct("_1INT_ST")
184 .field("frhost_bit8_int_st", &self.frhost_bit8_int_st())
185 .field("frhost_bit9_int_st", &self.frhost_bit9_int_st())
186 .field("frhost_bit10_int_st", &self.frhost_bit10_int_st())
187 .field("frhost_bit11_int_st", &self.frhost_bit11_int_st())
188 .field("frhost_bit12_int_st", &self.frhost_bit12_int_st())
189 .field("frhost_bit13_int_st", &self.frhost_bit13_int_st())
190 .field("frhost_bit14_int_st", &self.frhost_bit14_int_st())
191 .field("frhost_bit15_int_st", &self.frhost_bit15_int_st())
192 .field("slc1_rx_start_int_st", &self.slc1_rx_start_int_st())
193 .field("slc1_tx_start_int_st", &self.slc1_tx_start_int_st())
194 .field("slc1_rx_udf_int_st", &self.slc1_rx_udf_int_st())
195 .field("slc1_tx_ovf_int_st", &self.slc1_tx_ovf_int_st())
196 .field("slc1_token0_1to0_int_st", &self.slc1_token0_1to0_int_st())
197 .field("slc1_token1_1to0_int_st", &self.slc1_token1_1to0_int_st())
198 .field("slc1_tx_done_int_st", &self.slc1_tx_done_int_st())
199 .field("slc1_tx_suc_eof_int_st", &self.slc1_tx_suc_eof_int_st())
200 .field("slc1_rx_done_int_st", &self.slc1_rx_done_int_st())
201 .field("slc1_rx_eof_int_st", &self.slc1_rx_eof_int_st())
202 .field("slc1_tohost_int_st", &self.slc1_tohost_int_st())
203 .field("slc1_tx_dscr_err_int_st", &self.slc1_tx_dscr_err_int_st())
204 .field("slc1_rx_dscr_err_int_st", &self.slc1_rx_dscr_err_int_st())
205 .field(
206 "slc1_tx_dscr_empty_int_st",
207 &self.slc1_tx_dscr_empty_int_st(),
208 )
209 .field("slc1_host_rd_ack_int_st", &self.slc1_host_rd_ack_int_st())
210 .field(
211 "slc1_wr_retry_done_int_st",
212 &self.slc1_wr_retry_done_int_st(),
213 )
214 .field("slc1_tx_err_eof_int_st", &self.slc1_tx_err_eof_int_st())
215 .finish()
216 }
217}
218#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`_1int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
219pub struct _1INT_ST_SPEC;
220impl crate::RegisterSpec for _1INT_ST_SPEC {
221 type Ux = u32;
222}
223#[doc = "`read()` method returns [`_1int_st::R`](R) reader structure"]
224impl crate::Readable for _1INT_ST_SPEC {}
225#[doc = "`reset()` method sets _1INT_ST to value 0"]
226impl crate::Resettable for _1INT_ST_SPEC {
227 const RESET_VALUE: u32 = 0;
228}