esp32/sens/
sar_mem_wr_ctrl.rs

1#[doc = "Register `SAR_MEM_WR_CTRL` reader"]
2pub type R = crate::R<SAR_MEM_WR_CTRL_SPEC>;
3#[doc = "Register `SAR_MEM_WR_CTRL` writer"]
4pub type W = crate::W<SAR_MEM_WR_CTRL_SPEC>;
5#[doc = "Field `MEM_WR_ADDR_INIT` reader - "]
6pub type MEM_WR_ADDR_INIT_R = crate::FieldReader<u16>;
7#[doc = "Field `MEM_WR_ADDR_INIT` writer - "]
8pub type MEM_WR_ADDR_INIT_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
9#[doc = "Field `MEM_WR_ADDR_SIZE` reader - "]
10pub type MEM_WR_ADDR_SIZE_R = crate::FieldReader<u16>;
11#[doc = "Field `MEM_WR_ADDR_SIZE` writer - "]
12pub type MEM_WR_ADDR_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
13#[doc = "Field `RTC_MEM_WR_OFFST_CLR` writer - "]
14pub type RTC_MEM_WR_OFFST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
15impl R {
16    #[doc = "Bits 0:10"]
17    #[inline(always)]
18    pub fn mem_wr_addr_init(&self) -> MEM_WR_ADDR_INIT_R {
19        MEM_WR_ADDR_INIT_R::new((self.bits & 0x07ff) as u16)
20    }
21    #[doc = "Bits 11:21"]
22    #[inline(always)]
23    pub fn mem_wr_addr_size(&self) -> MEM_WR_ADDR_SIZE_R {
24        MEM_WR_ADDR_SIZE_R::new(((self.bits >> 11) & 0x07ff) as u16)
25    }
26}
27#[cfg(feature = "impl-register-debug")]
28impl core::fmt::Debug for R {
29    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30        f.debug_struct("SAR_MEM_WR_CTRL")
31            .field("mem_wr_addr_init", &self.mem_wr_addr_init())
32            .field("mem_wr_addr_size", &self.mem_wr_addr_size())
33            .finish()
34    }
35}
36impl W {
37    #[doc = "Bits 0:10"]
38    #[inline(always)]
39    pub fn mem_wr_addr_init(&mut self) -> MEM_WR_ADDR_INIT_W<SAR_MEM_WR_CTRL_SPEC> {
40        MEM_WR_ADDR_INIT_W::new(self, 0)
41    }
42    #[doc = "Bits 11:21"]
43    #[inline(always)]
44    pub fn mem_wr_addr_size(&mut self) -> MEM_WR_ADDR_SIZE_W<SAR_MEM_WR_CTRL_SPEC> {
45        MEM_WR_ADDR_SIZE_W::new(self, 11)
46    }
47    #[doc = "Bit 22"]
48    #[inline(always)]
49    pub fn rtc_mem_wr_offst_clr(&mut self) -> RTC_MEM_WR_OFFST_CLR_W<SAR_MEM_WR_CTRL_SPEC> {
50        RTC_MEM_WR_OFFST_CLR_W::new(self, 22)
51    }
52}
53#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_mem_wr_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_mem_wr_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
54pub struct SAR_MEM_WR_CTRL_SPEC;
55impl crate::RegisterSpec for SAR_MEM_WR_CTRL_SPEC {
56    type Ux = u32;
57}
58#[doc = "`read()` method returns [`sar_mem_wr_ctrl::R`](R) reader structure"]
59impl crate::Readable for SAR_MEM_WR_CTRL_SPEC {}
60#[doc = "`write(|w| ..)` method takes [`sar_mem_wr_ctrl::W`](W) writer structure"]
61impl crate::Writable for SAR_MEM_WR_CTRL_SPEC {
62    type Safety = crate::Unsafe;
63    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
64    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
65}
66#[doc = "`reset()` method sets SAR_MEM_WR_CTRL to value 0x0010_0200"]
67impl crate::Resettable for SAR_MEM_WR_CTRL_SPEC {
68    const RESET_VALUE: u32 = 0x0010_0200;
69}
esp32/sens/sar_mem_wr_ctrl.rs

esp32/sens/
sar_mem_wr_ctrl.rs
