1#[doc = "Register `CLKDIV` reader"]
2pub type R = crate::R<CLKDIV_SPEC>;
3#[doc = "Register `CLKDIV` writer"]
4pub type W = crate::W<CLKDIV_SPEC>;
5#[doc = "Field `CLK_DIVIDER0` reader - Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
6pub type CLK_DIVIDER0_R = crate::FieldReader;
7#[doc = "Field `CLK_DIVIDER0` writer - Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
8pub type CLK_DIVIDER0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `CLK_DIVIDER1` reader - Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
10pub type CLK_DIVIDER1_R = crate::FieldReader;
11#[doc = "Field `CLK_DIVIDER1` writer - Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
12pub type CLK_DIVIDER1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `CLK_DIVIDER2` reader - Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
14pub type CLK_DIVIDER2_R = crate::FieldReader;
15#[doc = "Field `CLK_DIVIDER2` writer - Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
16pub type CLK_DIVIDER2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17#[doc = "Field `CLK_DIVIDER3` reader - Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
18pub type CLK_DIVIDER3_R = crate::FieldReader;
19#[doc = "Field `CLK_DIVIDER3` writer - Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
20pub type CLK_DIVIDER3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
21impl R {
22 #[doc = "Bits 0:7 - Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
23 #[inline(always)]
24 pub fn clk_divider0(&self) -> CLK_DIVIDER0_R {
25 CLK_DIVIDER0_R::new((self.bits & 0xff) as u8)
26 }
27 #[doc = "Bits 8:15 - Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
28 #[inline(always)]
29 pub fn clk_divider1(&self) -> CLK_DIVIDER1_R {
30 CLK_DIVIDER1_R::new(((self.bits >> 8) & 0xff) as u8)
31 }
32 #[doc = "Bits 16:23 - Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
33 #[inline(always)]
34 pub fn clk_divider2(&self) -> CLK_DIVIDER2_R {
35 CLK_DIVIDER2_R::new(((self.bits >> 16) & 0xff) as u8)
36 }
37 #[doc = "Bits 24:31 - Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
38 #[inline(always)]
39 pub fn clk_divider3(&self) -> CLK_DIVIDER3_R {
40 CLK_DIVIDER3_R::new(((self.bits >> 24) & 0xff) as u8)
41 }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46 f.debug_struct("CLKDIV")
47 .field("clk_divider0", &self.clk_divider0())
48 .field("clk_divider1", &self.clk_divider1())
49 .field("clk_divider2", &self.clk_divider2())
50 .field("clk_divider3", &self.clk_divider3())
51 .finish()
52 }
53}
54impl W {
55 #[doc = "Bits 0:7 - Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
56 #[inline(always)]
57 pub fn clk_divider0(&mut self) -> CLK_DIVIDER0_W<CLKDIV_SPEC> {
58 CLK_DIVIDER0_W::new(self, 0)
59 }
60 #[doc = "Bits 8:15 - Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
61 #[inline(always)]
62 pub fn clk_divider1(&mut self) -> CLK_DIVIDER1_W<CLKDIV_SPEC> {
63 CLK_DIVIDER1_W::new(self, 8)
64 }
65 #[doc = "Bits 16:23 - Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
66 #[inline(always)]
67 pub fn clk_divider2(&mut self) -> CLK_DIVIDER2_W<CLKDIV_SPEC> {
68 CLK_DIVIDER2_W::new(self, 16)
69 }
70 #[doc = "Bits 24:31 - Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
71 #[inline(always)]
72 pub fn clk_divider3(&mut self) -> CLK_DIVIDER3_W<CLKDIV_SPEC> {
73 CLK_DIVIDER3_W::new(self, 24)
74 }
75}
76#[doc = "Clock divider configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct CLKDIV_SPEC;
78impl crate::RegisterSpec for CLKDIV_SPEC {
79 type Ux = u32;
80}
81#[doc = "`read()` method returns [`clkdiv::R`](R) reader structure"]
82impl crate::Readable for CLKDIV_SPEC {}
83#[doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"]
84impl crate::Writable for CLKDIV_SPEC {
85 type Safety = crate::Unsafe;
86 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
87 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
88}
89#[doc = "`reset()` method sets CLKDIV to value 0"]
90impl crate::Resettable for CLKDIV_SPEC {
91 const RESET_VALUE: u32 = 0;
92}