esp32/rtc_cntl/
sdio_conf.rs

1#[doc = "Register `SDIO_CONF` reader"]
2pub type R = crate::R<SDIO_CONF_SPEC>;
3#[doc = "Register `SDIO_CONF` writer"]
4pub type W = crate::W<SDIO_CONF_SPEC>;
5#[doc = "Field `SDIO_PD_EN` reader - power down SDIO_REG in sleep. Only active when reg_sdio_force = 0"]
6pub type SDIO_PD_EN_R = crate::BitReader;
7#[doc = "Field `SDIO_PD_EN` writer - power down SDIO_REG in sleep. Only active when reg_sdio_force = 0"]
8pub type SDIO_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SDIO_FORCE` reader - 1: use SW option to control SDIO_REG 0: use state machine"]
10pub type SDIO_FORCE_R = crate::BitReader;
11#[doc = "Field `SDIO_FORCE` writer - 1: use SW option to control SDIO_REG 0: use state machine"]
12pub type SDIO_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SDIO_TIEH` reader - SW option for SDIO_TIEH. Only active when reg_sdio_force = 1"]
14pub type SDIO_TIEH_R = crate::BitReader;
15#[doc = "Field `SDIO_TIEH` writer - SW option for SDIO_TIEH. Only active when reg_sdio_force = 1"]
16pub type SDIO_TIEH_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `REG1P8_READY` reader - read only register for REG1P8_READY"]
18pub type REG1P8_READY_R = crate::BitReader;
19#[doc = "Field `DREFL_SDIO` reader - SW option for DREFL_SDIO. Only active when reg_sdio_force = 1"]
20pub type DREFL_SDIO_R = crate::FieldReader;
21#[doc = "Field `DREFL_SDIO` writer - SW option for DREFL_SDIO. Only active when reg_sdio_force = 1"]
22pub type DREFL_SDIO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
23#[doc = "Field `DREFM_SDIO` reader - SW option for DREFM_SDIO. Only active when reg_sdio_force = 1"]
24pub type DREFM_SDIO_R = crate::FieldReader;
25#[doc = "Field `DREFM_SDIO` writer - SW option for DREFM_SDIO. Only active when reg_sdio_force = 1"]
26pub type DREFM_SDIO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
27#[doc = "Field `DREFH_SDIO` reader - SW option for DREFH_SDIO. Only active when reg_sdio_force = 1"]
28pub type DREFH_SDIO_R = crate::FieldReader;
29#[doc = "Field `DREFH_SDIO` writer - SW option for DREFH_SDIO. Only active when reg_sdio_force = 1"]
30pub type DREFH_SDIO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
31#[doc = "Field `XPD_SDIO` reader - SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1"]
32pub type XPD_SDIO_R = crate::BitReader;
33#[doc = "Field `XPD_SDIO` writer - SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1"]
34pub type XPD_SDIO_W<'a, REG> = crate::BitWriter<'a, REG>;
35impl R {
36    #[doc = "Bit 21 - power down SDIO_REG in sleep. Only active when reg_sdio_force = 0"]
37    #[inline(always)]
38    pub fn sdio_pd_en(&self) -> SDIO_PD_EN_R {
39        SDIO_PD_EN_R::new(((self.bits >> 21) & 1) != 0)
40    }
41    #[doc = "Bit 22 - 1: use SW option to control SDIO_REG 0: use state machine"]
42    #[inline(always)]
43    pub fn sdio_force(&self) -> SDIO_FORCE_R {
44        SDIO_FORCE_R::new(((self.bits >> 22) & 1) != 0)
45    }
46    #[doc = "Bit 23 - SW option for SDIO_TIEH. Only active when reg_sdio_force = 1"]
47    #[inline(always)]
48    pub fn sdio_tieh(&self) -> SDIO_TIEH_R {
49        SDIO_TIEH_R::new(((self.bits >> 23) & 1) != 0)
50    }
51    #[doc = "Bit 24 - read only register for REG1P8_READY"]
52    #[inline(always)]
53    pub fn reg1p8_ready(&self) -> REG1P8_READY_R {
54        REG1P8_READY_R::new(((self.bits >> 24) & 1) != 0)
55    }
56    #[doc = "Bits 25:26 - SW option for DREFL_SDIO. Only active when reg_sdio_force = 1"]
57    #[inline(always)]
58    pub fn drefl_sdio(&self) -> DREFL_SDIO_R {
59        DREFL_SDIO_R::new(((self.bits >> 25) & 3) as u8)
60    }
61    #[doc = "Bits 27:28 - SW option for DREFM_SDIO. Only active when reg_sdio_force = 1"]
62    #[inline(always)]
63    pub fn drefm_sdio(&self) -> DREFM_SDIO_R {
64        DREFM_SDIO_R::new(((self.bits >> 27) & 3) as u8)
65    }
66    #[doc = "Bits 29:30 - SW option for DREFH_SDIO. Only active when reg_sdio_force = 1"]
67    #[inline(always)]
68    pub fn drefh_sdio(&self) -> DREFH_SDIO_R {
69        DREFH_SDIO_R::new(((self.bits >> 29) & 3) as u8)
70    }
71    #[doc = "Bit 31 - SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1"]
72    #[inline(always)]
73    pub fn xpd_sdio(&self) -> XPD_SDIO_R {
74        XPD_SDIO_R::new(((self.bits >> 31) & 1) != 0)
75    }
76}
77#[cfg(feature = "impl-register-debug")]
78impl core::fmt::Debug for R {
79    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
80        f.debug_struct("SDIO_CONF")
81            .field("sdio_pd_en", &self.sdio_pd_en())
82            .field("sdio_force", &self.sdio_force())
83            .field("sdio_tieh", &self.sdio_tieh())
84            .field("reg1p8_ready", &self.reg1p8_ready())
85            .field("drefl_sdio", &self.drefl_sdio())
86            .field("drefm_sdio", &self.drefm_sdio())
87            .field("drefh_sdio", &self.drefh_sdio())
88            .field("xpd_sdio", &self.xpd_sdio())
89            .finish()
90    }
91}
92impl W {
93    #[doc = "Bit 21 - power down SDIO_REG in sleep. Only active when reg_sdio_force = 0"]
94    #[inline(always)]
95    pub fn sdio_pd_en(&mut self) -> SDIO_PD_EN_W<SDIO_CONF_SPEC> {
96        SDIO_PD_EN_W::new(self, 21)
97    }
98    #[doc = "Bit 22 - 1: use SW option to control SDIO_REG 0: use state machine"]
99    #[inline(always)]
100    pub fn sdio_force(&mut self) -> SDIO_FORCE_W<SDIO_CONF_SPEC> {
101        SDIO_FORCE_W::new(self, 22)
102    }
103    #[doc = "Bit 23 - SW option for SDIO_TIEH. Only active when reg_sdio_force = 1"]
104    #[inline(always)]
105    pub fn sdio_tieh(&mut self) -> SDIO_TIEH_W<SDIO_CONF_SPEC> {
106        SDIO_TIEH_W::new(self, 23)
107    }
108    #[doc = "Bits 25:26 - SW option for DREFL_SDIO. Only active when reg_sdio_force = 1"]
109    #[inline(always)]
110    pub fn drefl_sdio(&mut self) -> DREFL_SDIO_W<SDIO_CONF_SPEC> {
111        DREFL_SDIO_W::new(self, 25)
112    }
113    #[doc = "Bits 27:28 - SW option for DREFM_SDIO. Only active when reg_sdio_force = 1"]
114    #[inline(always)]
115    pub fn drefm_sdio(&mut self) -> DREFM_SDIO_W<SDIO_CONF_SPEC> {
116        DREFM_SDIO_W::new(self, 27)
117    }
118    #[doc = "Bits 29:30 - SW option for DREFH_SDIO. Only active when reg_sdio_force = 1"]
119    #[inline(always)]
120    pub fn drefh_sdio(&mut self) -> DREFH_SDIO_W<SDIO_CONF_SPEC> {
121        DREFH_SDIO_W::new(self, 29)
122    }
123    #[doc = "Bit 31 - SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1"]
124    #[inline(always)]
125    pub fn xpd_sdio(&mut self) -> XPD_SDIO_W<SDIO_CONF_SPEC> {
126        XPD_SDIO_W::new(self, 31)
127    }
128}
129#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`sdio_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdio_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
130pub struct SDIO_CONF_SPEC;
131impl crate::RegisterSpec for SDIO_CONF_SPEC {
132    type Ux = u32;
133}
134#[doc = "`read()` method returns [`sdio_conf::R`](R) reader structure"]
135impl crate::Readable for SDIO_CONF_SPEC {}
136#[doc = "`write(|w| ..)` method takes [`sdio_conf::W`](W) writer structure"]
137impl crate::Writable for SDIO_CONF_SPEC {
138    type Safety = crate::Unsafe;
139    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
140    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
141}
142#[doc = "`reset()` method sets SDIO_CONF to value 0x02a0_0000"]
143impl crate::Resettable for SDIO_CONF_SPEC {
144    const RESET_VALUE: u32 = 0x02a0_0000;
145}
esp32/rtc_cntl/sdio_conf.rs

esp32/rtc_cntl/
sdio_conf.rs
