esp32/rtc_cntl/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `SLP_WAKEUP` writer - Clear sleep wakeup interrupt state"]
4pub type SLP_WAKEUP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `SLP_REJECT` writer - Clear sleep reject interrupt state"]
6pub type SLP_REJECT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `SDIO_IDLE` writer - Clear SDIO idle interrupt state"]
8pub type SDIO_IDLE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `WDT` writer - Clear RTC WDT interrupt state"]
10pub type WDT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `TIME_VALID` writer - Clear RTC time valid interrupt state"]
12pub type TIME_VALID_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `SAR` writer - Clear ULP-coprocessor interrupt state"]
14pub type SAR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `TOUCH` writer - Clear touch interrupt state"]
16pub type TOUCH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `BROWN_OUT` writer - Clear brown out interrupt state"]
18pub type BROWN_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `MAIN_TIMER` writer - Clear RTC main timer interrupt state"]
20pub type MAIN_TIMER_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[cfg(feature = "impl-register-debug")]
22impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
23    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
24        write!(f, "(not readable)")
25    }
26}
27impl W {
28    #[doc = "Bit 0 - Clear sleep wakeup interrupt state"]
29    #[inline(always)]
30    pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<INT_CLR_SPEC> {
31        SLP_WAKEUP_W::new(self, 0)
32    }
33    #[doc = "Bit 1 - Clear sleep reject interrupt state"]
34    #[inline(always)]
35    pub fn slp_reject(&mut self) -> SLP_REJECT_W<INT_CLR_SPEC> {
36        SLP_REJECT_W::new(self, 1)
37    }
38    #[doc = "Bit 2 - Clear SDIO idle interrupt state"]
39    #[inline(always)]
40    pub fn sdio_idle(&mut self) -> SDIO_IDLE_W<INT_CLR_SPEC> {
41        SDIO_IDLE_W::new(self, 2)
42    }
43    #[doc = "Bit 3 - Clear RTC WDT interrupt state"]
44    #[inline(always)]
45    pub fn wdt(&mut self) -> WDT_W<INT_CLR_SPEC> {
46        WDT_W::new(self, 3)
47    }
48    #[doc = "Bit 4 - Clear RTC time valid interrupt state"]
49    #[inline(always)]
50    pub fn time_valid(&mut self) -> TIME_VALID_W<INT_CLR_SPEC> {
51        TIME_VALID_W::new(self, 4)
52    }
53    #[doc = "Bit 5 - Clear ULP-coprocessor interrupt state"]
54    #[inline(always)]
55    pub fn sar(&mut self) -> SAR_W<INT_CLR_SPEC> {
56        SAR_W::new(self, 5)
57    }
58    #[doc = "Bit 6 - Clear touch interrupt state"]
59    #[inline(always)]
60    pub fn touch(&mut self) -> TOUCH_W<INT_CLR_SPEC> {
61        TOUCH_W::new(self, 6)
62    }
63    #[doc = "Bit 7 - Clear brown out interrupt state"]
64    #[inline(always)]
65    pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_CLR_SPEC> {
66        BROWN_OUT_W::new(self, 7)
67    }
68    #[doc = "Bit 8 - Clear RTC main timer interrupt state"]
69    #[inline(always)]
70    pub fn main_timer(&mut self) -> MAIN_TIMER_W<INT_CLR_SPEC> {
71        MAIN_TIMER_W::new(self, 8)
72    }
73}
74#[doc = "\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
75pub struct INT_CLR_SPEC;
76impl crate::RegisterSpec for INT_CLR_SPEC {
77    type Ux = u32;
78}
79#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
80impl crate::Writable for INT_CLR_SPEC {
81    type Safety = crate::Unsafe;
82    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
83    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01ff;
84}
85#[doc = "`reset()` method sets INT_CLR to value 0"]
86impl crate::Resettable for INT_CLR_SPEC {
87    const RESET_VALUE: u32 = 0;
88}
esp32/rtc_cntl/int_clr.rs

esp32/rtc_cntl/
int_clr.rs
