esp32/hinf/
cfg_data7.rs

1#[doc = "Register `CFG_DATA7` reader"]
2pub type R = crate::R<CFG_DATA7_SPEC>;
3#[doc = "Register `CFG_DATA7` writer"]
4pub type W = crate::W<CFG_DATA7_SPEC>;
5#[doc = "Field `PIN_STATE` reader - "]
6pub type PIN_STATE_R = crate::FieldReader;
7#[doc = "Field `PIN_STATE` writer - "]
8pub type PIN_STATE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `CHIP_STATE` reader - "]
10pub type CHIP_STATE_R = crate::FieldReader;
11#[doc = "Field `CHIP_STATE` writer - "]
12pub type CHIP_STATE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `SDIO_RST` reader - "]
14pub type SDIO_RST_R = crate::BitReader;
15#[doc = "Field `SDIO_RST` writer - "]
16pub type SDIO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SDIO_IOREADY0` reader - "]
18pub type SDIO_IOREADY0_R = crate::BitReader;
19#[doc = "Field `SDIO_IOREADY0` writer - "]
20pub type SDIO_IOREADY0_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bits 0:7"]
23    #[inline(always)]
24    pub fn pin_state(&self) -> PIN_STATE_R {
25        PIN_STATE_R::new((self.bits & 0xff) as u8)
26    }
27    #[doc = "Bits 8:15"]
28    #[inline(always)]
29    pub fn chip_state(&self) -> CHIP_STATE_R {
30        CHIP_STATE_R::new(((self.bits >> 8) & 0xff) as u8)
31    }
32    #[doc = "Bit 16"]
33    #[inline(always)]
34    pub fn sdio_rst(&self) -> SDIO_RST_R {
35        SDIO_RST_R::new(((self.bits >> 16) & 1) != 0)
36    }
37    #[doc = "Bit 17"]
38    #[inline(always)]
39    pub fn sdio_ioready0(&self) -> SDIO_IOREADY0_R {
40        SDIO_IOREADY0_R::new(((self.bits >> 17) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("CFG_DATA7")
47            .field("pin_state", &self.pin_state())
48            .field("chip_state", &self.chip_state())
49            .field("sdio_rst", &self.sdio_rst())
50            .field("sdio_ioready0", &self.sdio_ioready0())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bits 0:7"]
56    #[inline(always)]
57    pub fn pin_state(&mut self) -> PIN_STATE_W<CFG_DATA7_SPEC> {
58        PIN_STATE_W::new(self, 0)
59    }
60    #[doc = "Bits 8:15"]
61    #[inline(always)]
62    pub fn chip_state(&mut self) -> CHIP_STATE_W<CFG_DATA7_SPEC> {
63        CHIP_STATE_W::new(self, 8)
64    }
65    #[doc = "Bit 16"]
66    #[inline(always)]
67    pub fn sdio_rst(&mut self) -> SDIO_RST_W<CFG_DATA7_SPEC> {
68        SDIO_RST_W::new(self, 16)
69    }
70    #[doc = "Bit 17"]
71    #[inline(always)]
72    pub fn sdio_ioready0(&mut self) -> SDIO_IOREADY0_W<CFG_DATA7_SPEC> {
73        SDIO_IOREADY0_W::new(self, 17)
74    }
75}
76#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_data7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_data7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct CFG_DATA7_SPEC;
78impl crate::RegisterSpec for CFG_DATA7_SPEC {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`cfg_data7::R`](R) reader structure"]
82impl crate::Readable for CFG_DATA7_SPEC {}
83#[doc = "`write(|w| ..)` method takes [`cfg_data7::W`](W) writer structure"]
84impl crate::Writable for CFG_DATA7_SPEC {
85    type Safety = crate::Unsafe;
86    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
87    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
88}
89#[doc = "`reset()` method sets CFG_DATA7 to value 0x0002_0000"]
90impl crate::Resettable for CFG_DATA7_SPEC {
91    const RESET_VALUE: u32 = 0x0002_0000;
92}
esp32/hinf/cfg_data7.rs

esp32/hinf/
cfg_data7.rs
