1#[doc = "Register `PERIP_RST_EN` reader"]
2pub type R = crate::R<PERIP_RST_EN_SPEC>;
3#[doc = "Register `PERIP_RST_EN` writer"]
4pub type W = crate::W<PERIP_RST_EN_SPEC>;
5#[doc = "Field `TIMERS_RST` reader - "]
6pub type TIMERS_RST_R = crate::BitReader;
7#[doc = "Field `TIMERS_RST` writer - "]
8pub type TIMERS_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SPI01_RST` reader - "]
10pub type SPI01_RST_R = crate::BitReader;
11#[doc = "Field `SPI01_RST` writer - "]
12pub type SPI01_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `UART_RST` reader - "]
14pub type UART_RST_R = crate::BitReader;
15#[doc = "Field `UART_RST` writer - "]
16pub type UART_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `WDG_RST` reader - "]
18pub type WDG_RST_R = crate::BitReader;
19#[doc = "Field `WDG_RST` writer - "]
20pub type WDG_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `I2S0_RST` reader - "]
22pub type I2S0_RST_R = crate::BitReader;
23#[doc = "Field `I2S0_RST` writer - "]
24pub type I2S0_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `UART1_RST` reader - "]
26pub type UART1_RST_R = crate::BitReader;
27#[doc = "Field `UART1_RST` writer - "]
28pub type UART1_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SPI2_RST` reader - "]
30pub type SPI2_RST_R = crate::BitReader;
31#[doc = "Field `SPI2_RST` writer - "]
32pub type SPI2_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `I2C0_EXT0_RST` reader - "]
34pub type I2C0_EXT0_RST_R = crate::BitReader;
35#[doc = "Field `I2C0_EXT0_RST` writer - "]
36pub type I2C0_EXT0_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `UHCI0_RST` reader - "]
38pub type UHCI0_RST_R = crate::BitReader;
39#[doc = "Field `UHCI0_RST` writer - "]
40pub type UHCI0_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `RMT_RST` reader - "]
42pub type RMT_RST_R = crate::BitReader;
43#[doc = "Field `RMT_RST` writer - "]
44pub type RMT_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `PCNT_RST` reader - "]
46pub type PCNT_RST_R = crate::BitReader;
47#[doc = "Field `PCNT_RST` writer - "]
48pub type PCNT_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `LEDC_RST` reader - "]
50pub type LEDC_RST_R = crate::BitReader;
51#[doc = "Field `LEDC_RST` writer - "]
52pub type LEDC_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `UHCI1_RST` reader - "]
54pub type UHCI1_RST_R = crate::BitReader;
55#[doc = "Field `UHCI1_RST` writer - "]
56pub type UHCI1_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `TIMERGROUP_RST` reader - "]
58pub type TIMERGROUP_RST_R = crate::BitReader;
59#[doc = "Field `TIMERGROUP_RST` writer - "]
60pub type TIMERGROUP_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `EFUSE_RST` reader - "]
62pub type EFUSE_RST_R = crate::BitReader;
63#[doc = "Field `EFUSE_RST` writer - "]
64pub type EFUSE_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `TIMERGROUP1_RST` reader - "]
66pub type TIMERGROUP1_RST_R = crate::BitReader;
67#[doc = "Field `TIMERGROUP1_RST` writer - "]
68pub type TIMERGROUP1_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `SPI3_RST` reader - "]
70pub type SPI3_RST_R = crate::BitReader;
71#[doc = "Field `SPI3_RST` writer - "]
72pub type SPI3_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `PWM0_RST` reader - "]
74pub type PWM0_RST_R = crate::BitReader;
75#[doc = "Field `PWM0_RST` writer - "]
76pub type PWM0_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `I2C_EXT1_RST` reader - "]
78pub type I2C_EXT1_RST_R = crate::BitReader;
79#[doc = "Field `I2C_EXT1_RST` writer - "]
80pub type I2C_EXT1_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `TWAI_RST` reader - "]
82pub type TWAI_RST_R = crate::BitReader;
83#[doc = "Field `TWAI_RST` writer - "]
84pub type TWAI_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `PWM1_RST` reader - "]
86pub type PWM1_RST_R = crate::BitReader;
87#[doc = "Field `PWM1_RST` writer - "]
88pub type PWM1_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `I2S1_RST` reader - "]
90pub type I2S1_RST_R = crate::BitReader;
91#[doc = "Field `I2S1_RST` writer - "]
92pub type I2S1_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `SPI_DMA_RST` reader - "]
94pub type SPI_DMA_RST_R = crate::BitReader;
95#[doc = "Field `SPI_DMA_RST` writer - "]
96pub type SPI_DMA_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `UART2_RST` reader - "]
98pub type UART2_RST_R = crate::BitReader;
99#[doc = "Field `UART2_RST` writer - "]
100pub type UART2_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
101#[doc = "Field `UART_MEM_RST` reader - "]
102pub type UART_MEM_RST_R = crate::BitReader;
103#[doc = "Field `UART_MEM_RST` writer - "]
104pub type UART_MEM_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
105#[doc = "Field `PWM2_RST` reader - "]
106pub type PWM2_RST_R = crate::BitReader;
107#[doc = "Field `PWM2_RST` writer - "]
108pub type PWM2_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
109#[doc = "Field `PWM3_RST` reader - "]
110pub type PWM3_RST_R = crate::BitReader;
111#[doc = "Field `PWM3_RST` writer - "]
112pub type PWM3_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
113impl R {
114 #[doc = "Bit 0"]
115 #[inline(always)]
116 pub fn timers_rst(&self) -> TIMERS_RST_R {
117 TIMERS_RST_R::new((self.bits & 1) != 0)
118 }
119 #[doc = "Bit 1"]
120 #[inline(always)]
121 pub fn spi01_rst(&self) -> SPI01_RST_R {
122 SPI01_RST_R::new(((self.bits >> 1) & 1) != 0)
123 }
124 #[doc = "Bit 2"]
125 #[inline(always)]
126 pub fn uart_rst(&self) -> UART_RST_R {
127 UART_RST_R::new(((self.bits >> 2) & 1) != 0)
128 }
129 #[doc = "Bit 3"]
130 #[inline(always)]
131 pub fn wdg_rst(&self) -> WDG_RST_R {
132 WDG_RST_R::new(((self.bits >> 3) & 1) != 0)
133 }
134 #[doc = "Bit 4"]
135 #[inline(always)]
136 pub fn i2s0_rst(&self) -> I2S0_RST_R {
137 I2S0_RST_R::new(((self.bits >> 4) & 1) != 0)
138 }
139 #[doc = "Bit 5"]
140 #[inline(always)]
141 pub fn uart1_rst(&self) -> UART1_RST_R {
142 UART1_RST_R::new(((self.bits >> 5) & 1) != 0)
143 }
144 #[doc = "Bit 6"]
145 #[inline(always)]
146 pub fn spi2_rst(&self) -> SPI2_RST_R {
147 SPI2_RST_R::new(((self.bits >> 6) & 1) != 0)
148 }
149 #[doc = "Bit 7"]
150 #[inline(always)]
151 pub fn i2c0_ext0_rst(&self) -> I2C0_EXT0_RST_R {
152 I2C0_EXT0_RST_R::new(((self.bits >> 7) & 1) != 0)
153 }
154 #[doc = "Bit 8"]
155 #[inline(always)]
156 pub fn uhci0_rst(&self) -> UHCI0_RST_R {
157 UHCI0_RST_R::new(((self.bits >> 8) & 1) != 0)
158 }
159 #[doc = "Bit 9"]
160 #[inline(always)]
161 pub fn rmt_rst(&self) -> RMT_RST_R {
162 RMT_RST_R::new(((self.bits >> 9) & 1) != 0)
163 }
164 #[doc = "Bit 10"]
165 #[inline(always)]
166 pub fn pcnt_rst(&self) -> PCNT_RST_R {
167 PCNT_RST_R::new(((self.bits >> 10) & 1) != 0)
168 }
169 #[doc = "Bit 11"]
170 #[inline(always)]
171 pub fn ledc_rst(&self) -> LEDC_RST_R {
172 LEDC_RST_R::new(((self.bits >> 11) & 1) != 0)
173 }
174 #[doc = "Bit 12"]
175 #[inline(always)]
176 pub fn uhci1_rst(&self) -> UHCI1_RST_R {
177 UHCI1_RST_R::new(((self.bits >> 12) & 1) != 0)
178 }
179 #[doc = "Bit 13"]
180 #[inline(always)]
181 pub fn timergroup_rst(&self) -> TIMERGROUP_RST_R {
182 TIMERGROUP_RST_R::new(((self.bits >> 13) & 1) != 0)
183 }
184 #[doc = "Bit 14"]
185 #[inline(always)]
186 pub fn efuse_rst(&self) -> EFUSE_RST_R {
187 EFUSE_RST_R::new(((self.bits >> 14) & 1) != 0)
188 }
189 #[doc = "Bit 15"]
190 #[inline(always)]
191 pub fn timergroup1_rst(&self) -> TIMERGROUP1_RST_R {
192 TIMERGROUP1_RST_R::new(((self.bits >> 15) & 1) != 0)
193 }
194 #[doc = "Bit 16"]
195 #[inline(always)]
196 pub fn spi3_rst(&self) -> SPI3_RST_R {
197 SPI3_RST_R::new(((self.bits >> 16) & 1) != 0)
198 }
199 #[doc = "Bit 17"]
200 #[inline(always)]
201 pub fn pwm0_rst(&self) -> PWM0_RST_R {
202 PWM0_RST_R::new(((self.bits >> 17) & 1) != 0)
203 }
204 #[doc = "Bit 18"]
205 #[inline(always)]
206 pub fn i2c_ext1_rst(&self) -> I2C_EXT1_RST_R {
207 I2C_EXT1_RST_R::new(((self.bits >> 18) & 1) != 0)
208 }
209 #[doc = "Bit 19"]
210 #[inline(always)]
211 pub fn twai_rst(&self) -> TWAI_RST_R {
212 TWAI_RST_R::new(((self.bits >> 19) & 1) != 0)
213 }
214 #[doc = "Bit 20"]
215 #[inline(always)]
216 pub fn pwm1_rst(&self) -> PWM1_RST_R {
217 PWM1_RST_R::new(((self.bits >> 20) & 1) != 0)
218 }
219 #[doc = "Bit 21"]
220 #[inline(always)]
221 pub fn i2s1_rst(&self) -> I2S1_RST_R {
222 I2S1_RST_R::new(((self.bits >> 21) & 1) != 0)
223 }
224 #[doc = "Bit 22"]
225 #[inline(always)]
226 pub fn spi_dma_rst(&self) -> SPI_DMA_RST_R {
227 SPI_DMA_RST_R::new(((self.bits >> 22) & 1) != 0)
228 }
229 #[doc = "Bit 23"]
230 #[inline(always)]
231 pub fn uart2_rst(&self) -> UART2_RST_R {
232 UART2_RST_R::new(((self.bits >> 23) & 1) != 0)
233 }
234 #[doc = "Bit 24"]
235 #[inline(always)]
236 pub fn uart_mem_rst(&self) -> UART_MEM_RST_R {
237 UART_MEM_RST_R::new(((self.bits >> 24) & 1) != 0)
238 }
239 #[doc = "Bit 25"]
240 #[inline(always)]
241 pub fn pwm2_rst(&self) -> PWM2_RST_R {
242 PWM2_RST_R::new(((self.bits >> 25) & 1) != 0)
243 }
244 #[doc = "Bit 26"]
245 #[inline(always)]
246 pub fn pwm3_rst(&self) -> PWM3_RST_R {
247 PWM3_RST_R::new(((self.bits >> 26) & 1) != 0)
248 }
249}
250#[cfg(feature = "impl-register-debug")]
251impl core::fmt::Debug for R {
252 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
253 f.debug_struct("PERIP_RST_EN")
254 .field("timers_rst", &self.timers_rst())
255 .field("spi01_rst", &self.spi01_rst())
256 .field("uart_rst", &self.uart_rst())
257 .field("wdg_rst", &self.wdg_rst())
258 .field("i2s0_rst", &self.i2s0_rst())
259 .field("uart1_rst", &self.uart1_rst())
260 .field("spi2_rst", &self.spi2_rst())
261 .field("i2c0_ext0_rst", &self.i2c0_ext0_rst())
262 .field("uhci0_rst", &self.uhci0_rst())
263 .field("rmt_rst", &self.rmt_rst())
264 .field("pcnt_rst", &self.pcnt_rst())
265 .field("ledc_rst", &self.ledc_rst())
266 .field("uhci1_rst", &self.uhci1_rst())
267 .field("timergroup_rst", &self.timergroup_rst())
268 .field("efuse_rst", &self.efuse_rst())
269 .field("timergroup1_rst", &self.timergroup1_rst())
270 .field("spi3_rst", &self.spi3_rst())
271 .field("pwm0_rst", &self.pwm0_rst())
272 .field("i2c_ext1_rst", &self.i2c_ext1_rst())
273 .field("twai_rst", &self.twai_rst())
274 .field("pwm1_rst", &self.pwm1_rst())
275 .field("i2s1_rst", &self.i2s1_rst())
276 .field("spi_dma_rst", &self.spi_dma_rst())
277 .field("uart2_rst", &self.uart2_rst())
278 .field("uart_mem_rst", &self.uart_mem_rst())
279 .field("pwm2_rst", &self.pwm2_rst())
280 .field("pwm3_rst", &self.pwm3_rst())
281 .finish()
282 }
283}
284impl W {
285 #[doc = "Bit 0"]
286 #[inline(always)]
287 pub fn timers_rst(&mut self) -> TIMERS_RST_W<PERIP_RST_EN_SPEC> {
288 TIMERS_RST_W::new(self, 0)
289 }
290 #[doc = "Bit 1"]
291 #[inline(always)]
292 pub fn spi01_rst(&mut self) -> SPI01_RST_W<PERIP_RST_EN_SPEC> {
293 SPI01_RST_W::new(self, 1)
294 }
295 #[doc = "Bit 2"]
296 #[inline(always)]
297 pub fn uart_rst(&mut self) -> UART_RST_W<PERIP_RST_EN_SPEC> {
298 UART_RST_W::new(self, 2)
299 }
300 #[doc = "Bit 3"]
301 #[inline(always)]
302 pub fn wdg_rst(&mut self) -> WDG_RST_W<PERIP_RST_EN_SPEC> {
303 WDG_RST_W::new(self, 3)
304 }
305 #[doc = "Bit 4"]
306 #[inline(always)]
307 pub fn i2s0_rst(&mut self) -> I2S0_RST_W<PERIP_RST_EN_SPEC> {
308 I2S0_RST_W::new(self, 4)
309 }
310 #[doc = "Bit 5"]
311 #[inline(always)]
312 pub fn uart1_rst(&mut self) -> UART1_RST_W<PERIP_RST_EN_SPEC> {
313 UART1_RST_W::new(self, 5)
314 }
315 #[doc = "Bit 6"]
316 #[inline(always)]
317 pub fn spi2_rst(&mut self) -> SPI2_RST_W<PERIP_RST_EN_SPEC> {
318 SPI2_RST_W::new(self, 6)
319 }
320 #[doc = "Bit 7"]
321 #[inline(always)]
322 pub fn i2c0_ext0_rst(&mut self) -> I2C0_EXT0_RST_W<PERIP_RST_EN_SPEC> {
323 I2C0_EXT0_RST_W::new(self, 7)
324 }
325 #[doc = "Bit 8"]
326 #[inline(always)]
327 pub fn uhci0_rst(&mut self) -> UHCI0_RST_W<PERIP_RST_EN_SPEC> {
328 UHCI0_RST_W::new(self, 8)
329 }
330 #[doc = "Bit 9"]
331 #[inline(always)]
332 pub fn rmt_rst(&mut self) -> RMT_RST_W<PERIP_RST_EN_SPEC> {
333 RMT_RST_W::new(self, 9)
334 }
335 #[doc = "Bit 10"]
336 #[inline(always)]
337 pub fn pcnt_rst(&mut self) -> PCNT_RST_W<PERIP_RST_EN_SPEC> {
338 PCNT_RST_W::new(self, 10)
339 }
340 #[doc = "Bit 11"]
341 #[inline(always)]
342 pub fn ledc_rst(&mut self) -> LEDC_RST_W<PERIP_RST_EN_SPEC> {
343 LEDC_RST_W::new(self, 11)
344 }
345 #[doc = "Bit 12"]
346 #[inline(always)]
347 pub fn uhci1_rst(&mut self) -> UHCI1_RST_W<PERIP_RST_EN_SPEC> {
348 UHCI1_RST_W::new(self, 12)
349 }
350 #[doc = "Bit 13"]
351 #[inline(always)]
352 pub fn timergroup_rst(&mut self) -> TIMERGROUP_RST_W<PERIP_RST_EN_SPEC> {
353 TIMERGROUP_RST_W::new(self, 13)
354 }
355 #[doc = "Bit 14"]
356 #[inline(always)]
357 pub fn efuse_rst(&mut self) -> EFUSE_RST_W<PERIP_RST_EN_SPEC> {
358 EFUSE_RST_W::new(self, 14)
359 }
360 #[doc = "Bit 15"]
361 #[inline(always)]
362 pub fn timergroup1_rst(&mut self) -> TIMERGROUP1_RST_W<PERIP_RST_EN_SPEC> {
363 TIMERGROUP1_RST_W::new(self, 15)
364 }
365 #[doc = "Bit 16"]
366 #[inline(always)]
367 pub fn spi3_rst(&mut self) -> SPI3_RST_W<PERIP_RST_EN_SPEC> {
368 SPI3_RST_W::new(self, 16)
369 }
370 #[doc = "Bit 17"]
371 #[inline(always)]
372 pub fn pwm0_rst(&mut self) -> PWM0_RST_W<PERIP_RST_EN_SPEC> {
373 PWM0_RST_W::new(self, 17)
374 }
375 #[doc = "Bit 18"]
376 #[inline(always)]
377 pub fn i2c_ext1_rst(&mut self) -> I2C_EXT1_RST_W<PERIP_RST_EN_SPEC> {
378 I2C_EXT1_RST_W::new(self, 18)
379 }
380 #[doc = "Bit 19"]
381 #[inline(always)]
382 pub fn twai_rst(&mut self) -> TWAI_RST_W<PERIP_RST_EN_SPEC> {
383 TWAI_RST_W::new(self, 19)
384 }
385 #[doc = "Bit 20"]
386 #[inline(always)]
387 pub fn pwm1_rst(&mut self) -> PWM1_RST_W<PERIP_RST_EN_SPEC> {
388 PWM1_RST_W::new(self, 20)
389 }
390 #[doc = "Bit 21"]
391 #[inline(always)]
392 pub fn i2s1_rst(&mut self) -> I2S1_RST_W<PERIP_RST_EN_SPEC> {
393 I2S1_RST_W::new(self, 21)
394 }
395 #[doc = "Bit 22"]
396 #[inline(always)]
397 pub fn spi_dma_rst(&mut self) -> SPI_DMA_RST_W<PERIP_RST_EN_SPEC> {
398 SPI_DMA_RST_W::new(self, 22)
399 }
400 #[doc = "Bit 23"]
401 #[inline(always)]
402 pub fn uart2_rst(&mut self) -> UART2_RST_W<PERIP_RST_EN_SPEC> {
403 UART2_RST_W::new(self, 23)
404 }
405 #[doc = "Bit 24"]
406 #[inline(always)]
407 pub fn uart_mem_rst(&mut self) -> UART_MEM_RST_W<PERIP_RST_EN_SPEC> {
408 UART_MEM_RST_W::new(self, 24)
409 }
410 #[doc = "Bit 25"]
411 #[inline(always)]
412 pub fn pwm2_rst(&mut self) -> PWM2_RST_W<PERIP_RST_EN_SPEC> {
413 PWM2_RST_W::new(self, 25)
414 }
415 #[doc = "Bit 26"]
416 #[inline(always)]
417 pub fn pwm3_rst(&mut self) -> PWM3_RST_W<PERIP_RST_EN_SPEC> {
418 PWM3_RST_W::new(self, 26)
419 }
420}
421#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`perip_rst_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perip_rst_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
422pub struct PERIP_RST_EN_SPEC;
423impl crate::RegisterSpec for PERIP_RST_EN_SPEC {
424 type Ux = u32;
425}
426#[doc = "`read()` method returns [`perip_rst_en::R`](R) reader structure"]
427impl crate::Readable for PERIP_RST_EN_SPEC {}
428#[doc = "`write(|w| ..)` method takes [`perip_rst_en::W`](W) writer structure"]
429impl crate::Writable for PERIP_RST_EN_SPEC {
430 type Safety = crate::Unsafe;
431 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
432 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
433}
434#[doc = "`reset()` method sets PERIP_RST_EN to value 0"]
435impl crate::Resettable for PERIP_RST_EN_SPEC {
436 const RESET_VALUE: u32 = 0;
437}