1#[doc = "Register `_1INT_CLR` writer"]
2pub type W = crate::W<_1INT_CLR_SPEC>;
3#[doc = "Field `FRHOST_BIT8_INT_CLR` writer - "]
4pub type FRHOST_BIT8_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `FRHOST_BIT9_INT_CLR` writer - "]
6pub type FRHOST_BIT9_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `FRHOST_BIT10_INT_CLR` writer - "]
8pub type FRHOST_BIT10_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `FRHOST_BIT11_INT_CLR` writer - "]
10pub type FRHOST_BIT11_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `FRHOST_BIT12_INT_CLR` writer - "]
12pub type FRHOST_BIT12_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FRHOST_BIT13_INT_CLR` writer - "]
14pub type FRHOST_BIT13_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `FRHOST_BIT14_INT_CLR` writer - "]
16pub type FRHOST_BIT14_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FRHOST_BIT15_INT_CLR` writer - "]
18pub type FRHOST_BIT15_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `SLC1_RX_START_INT_CLR` writer - "]
20pub type SLC1_RX_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SLC1_TX_START_INT_CLR` writer - "]
22pub type SLC1_TX_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `SLC1_RX_UDF_INT_CLR` writer - "]
24pub type SLC1_RX_UDF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SLC1_TX_OVF_INT_CLR` writer - "]
26pub type SLC1_TX_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `SLC1_TOKEN0_1TO0_INT_CLR` writer - "]
28pub type SLC1_TOKEN0_1TO0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SLC1_TOKEN1_1TO0_INT_CLR` writer - "]
30pub type SLC1_TOKEN1_1TO0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `SLC1_TX_DONE_INT_CLR` writer - "]
32pub type SLC1_TX_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SLC1_TX_SUC_EOF_INT_CLR` writer - "]
34pub type SLC1_TX_SUC_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `SLC1_RX_DONE_INT_CLR` writer - "]
36pub type SLC1_RX_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `SLC1_RX_EOF_INT_CLR` writer - "]
38pub type SLC1_RX_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "Field `SLC1_TOHOST_INT_CLR` writer - "]
40pub type SLC1_TOHOST_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SLC1_TX_DSCR_ERR_INT_CLR` writer - "]
42pub type SLC1_TX_DSCR_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
43#[doc = "Field `SLC1_RX_DSCR_ERR_INT_CLR` writer - "]
44pub type SLC1_RX_DSCR_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `SLC1_TX_DSCR_EMPTY_INT_CLR` writer - "]
46pub type SLC1_TX_DSCR_EMPTY_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
47#[doc = "Field `SLC1_HOST_RD_ACK_INT_CLR` writer - "]
48pub type SLC1_HOST_RD_ACK_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `SLC1_WR_RETRY_DONE_INT_CLR` writer - "]
50pub type SLC1_WR_RETRY_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
51#[doc = "Field `SLC1_TX_ERR_EOF_INT_CLR` writer - "]
52pub type SLC1_TX_ERR_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[cfg(feature = "impl-register-debug")]
54impl core::fmt::Debug for crate::generic::Reg<_1INT_CLR_SPEC> {
55 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
56 write!(f, "(not readable)")
57 }
58}
59impl W {
60 #[doc = "Bit 0"]
61 #[inline(always)]
62 pub fn frhost_bit8_int_clr(&mut self) -> FRHOST_BIT8_INT_CLR_W<_1INT_CLR_SPEC> {
63 FRHOST_BIT8_INT_CLR_W::new(self, 0)
64 }
65 #[doc = "Bit 1"]
66 #[inline(always)]
67 pub fn frhost_bit9_int_clr(&mut self) -> FRHOST_BIT9_INT_CLR_W<_1INT_CLR_SPEC> {
68 FRHOST_BIT9_INT_CLR_W::new(self, 1)
69 }
70 #[doc = "Bit 2"]
71 #[inline(always)]
72 pub fn frhost_bit10_int_clr(&mut self) -> FRHOST_BIT10_INT_CLR_W<_1INT_CLR_SPEC> {
73 FRHOST_BIT10_INT_CLR_W::new(self, 2)
74 }
75 #[doc = "Bit 3"]
76 #[inline(always)]
77 pub fn frhost_bit11_int_clr(&mut self) -> FRHOST_BIT11_INT_CLR_W<_1INT_CLR_SPEC> {
78 FRHOST_BIT11_INT_CLR_W::new(self, 3)
79 }
80 #[doc = "Bit 4"]
81 #[inline(always)]
82 pub fn frhost_bit12_int_clr(&mut self) -> FRHOST_BIT12_INT_CLR_W<_1INT_CLR_SPEC> {
83 FRHOST_BIT12_INT_CLR_W::new(self, 4)
84 }
85 #[doc = "Bit 5"]
86 #[inline(always)]
87 pub fn frhost_bit13_int_clr(&mut self) -> FRHOST_BIT13_INT_CLR_W<_1INT_CLR_SPEC> {
88 FRHOST_BIT13_INT_CLR_W::new(self, 5)
89 }
90 #[doc = "Bit 6"]
91 #[inline(always)]
92 pub fn frhost_bit14_int_clr(&mut self) -> FRHOST_BIT14_INT_CLR_W<_1INT_CLR_SPEC> {
93 FRHOST_BIT14_INT_CLR_W::new(self, 6)
94 }
95 #[doc = "Bit 7"]
96 #[inline(always)]
97 pub fn frhost_bit15_int_clr(&mut self) -> FRHOST_BIT15_INT_CLR_W<_1INT_CLR_SPEC> {
98 FRHOST_BIT15_INT_CLR_W::new(self, 7)
99 }
100 #[doc = "Bit 8"]
101 #[inline(always)]
102 pub fn slc1_rx_start_int_clr(&mut self) -> SLC1_RX_START_INT_CLR_W<_1INT_CLR_SPEC> {
103 SLC1_RX_START_INT_CLR_W::new(self, 8)
104 }
105 #[doc = "Bit 9"]
106 #[inline(always)]
107 pub fn slc1_tx_start_int_clr(&mut self) -> SLC1_TX_START_INT_CLR_W<_1INT_CLR_SPEC> {
108 SLC1_TX_START_INT_CLR_W::new(self, 9)
109 }
110 #[doc = "Bit 10"]
111 #[inline(always)]
112 pub fn slc1_rx_udf_int_clr(&mut self) -> SLC1_RX_UDF_INT_CLR_W<_1INT_CLR_SPEC> {
113 SLC1_RX_UDF_INT_CLR_W::new(self, 10)
114 }
115 #[doc = "Bit 11"]
116 #[inline(always)]
117 pub fn slc1_tx_ovf_int_clr(&mut self) -> SLC1_TX_OVF_INT_CLR_W<_1INT_CLR_SPEC> {
118 SLC1_TX_OVF_INT_CLR_W::new(self, 11)
119 }
120 #[doc = "Bit 12"]
121 #[inline(always)]
122 pub fn slc1_token0_1to0_int_clr(&mut self) -> SLC1_TOKEN0_1TO0_INT_CLR_W<_1INT_CLR_SPEC> {
123 SLC1_TOKEN0_1TO0_INT_CLR_W::new(self, 12)
124 }
125 #[doc = "Bit 13"]
126 #[inline(always)]
127 pub fn slc1_token1_1to0_int_clr(&mut self) -> SLC1_TOKEN1_1TO0_INT_CLR_W<_1INT_CLR_SPEC> {
128 SLC1_TOKEN1_1TO0_INT_CLR_W::new(self, 13)
129 }
130 #[doc = "Bit 14"]
131 #[inline(always)]
132 pub fn slc1_tx_done_int_clr(&mut self) -> SLC1_TX_DONE_INT_CLR_W<_1INT_CLR_SPEC> {
133 SLC1_TX_DONE_INT_CLR_W::new(self, 14)
134 }
135 #[doc = "Bit 15"]
136 #[inline(always)]
137 pub fn slc1_tx_suc_eof_int_clr(&mut self) -> SLC1_TX_SUC_EOF_INT_CLR_W<_1INT_CLR_SPEC> {
138 SLC1_TX_SUC_EOF_INT_CLR_W::new(self, 15)
139 }
140 #[doc = "Bit 16"]
141 #[inline(always)]
142 pub fn slc1_rx_done_int_clr(&mut self) -> SLC1_RX_DONE_INT_CLR_W<_1INT_CLR_SPEC> {
143 SLC1_RX_DONE_INT_CLR_W::new(self, 16)
144 }
145 #[doc = "Bit 17"]
146 #[inline(always)]
147 pub fn slc1_rx_eof_int_clr(&mut self) -> SLC1_RX_EOF_INT_CLR_W<_1INT_CLR_SPEC> {
148 SLC1_RX_EOF_INT_CLR_W::new(self, 17)
149 }
150 #[doc = "Bit 18"]
151 #[inline(always)]
152 pub fn slc1_tohost_int_clr(&mut self) -> SLC1_TOHOST_INT_CLR_W<_1INT_CLR_SPEC> {
153 SLC1_TOHOST_INT_CLR_W::new(self, 18)
154 }
155 #[doc = "Bit 19"]
156 #[inline(always)]
157 pub fn slc1_tx_dscr_err_int_clr(&mut self) -> SLC1_TX_DSCR_ERR_INT_CLR_W<_1INT_CLR_SPEC> {
158 SLC1_TX_DSCR_ERR_INT_CLR_W::new(self, 19)
159 }
160 #[doc = "Bit 20"]
161 #[inline(always)]
162 pub fn slc1_rx_dscr_err_int_clr(&mut self) -> SLC1_RX_DSCR_ERR_INT_CLR_W<_1INT_CLR_SPEC> {
163 SLC1_RX_DSCR_ERR_INT_CLR_W::new(self, 20)
164 }
165 #[doc = "Bit 21"]
166 #[inline(always)]
167 pub fn slc1_tx_dscr_empty_int_clr(&mut self) -> SLC1_TX_DSCR_EMPTY_INT_CLR_W<_1INT_CLR_SPEC> {
168 SLC1_TX_DSCR_EMPTY_INT_CLR_W::new(self, 21)
169 }
170 #[doc = "Bit 22"]
171 #[inline(always)]
172 pub fn slc1_host_rd_ack_int_clr(&mut self) -> SLC1_HOST_RD_ACK_INT_CLR_W<_1INT_CLR_SPEC> {
173 SLC1_HOST_RD_ACK_INT_CLR_W::new(self, 22)
174 }
175 #[doc = "Bit 23"]
176 #[inline(always)]
177 pub fn slc1_wr_retry_done_int_clr(&mut self) -> SLC1_WR_RETRY_DONE_INT_CLR_W<_1INT_CLR_SPEC> {
178 SLC1_WR_RETRY_DONE_INT_CLR_W::new(self, 23)
179 }
180 #[doc = "Bit 24"]
181 #[inline(always)]
182 pub fn slc1_tx_err_eof_int_clr(&mut self) -> SLC1_TX_ERR_EOF_INT_CLR_W<_1INT_CLR_SPEC> {
183 SLC1_TX_ERR_EOF_INT_CLR_W::new(self, 24)
184 }
185}
186#[doc = "\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`_1int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
187pub struct _1INT_CLR_SPEC;
188impl crate::RegisterSpec for _1INT_CLR_SPEC {
189 type Ux = u32;
190}
191#[doc = "`write(|w| ..)` method takes [`_1int_clr::W`](W) writer structure"]
192impl crate::Writable for _1INT_CLR_SPEC {
193 type Safety = crate::Unsafe;
194 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
195 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
196}
197#[doc = "`reset()` method sets _1INT_CLR to value 0"]
198impl crate::Resettable for _1INT_CLR_SPEC {
199 const RESET_VALUE: u32 = 0;
200}