esp32/dport/
iram_dram_ahb_sel.rs

1#[doc = "Register `IRAM_DRAM_AHB_SEL` reader"]
2pub type R = crate::R<IRAM_DRAM_AHB_SEL_SPEC>;
3#[doc = "Register `IRAM_DRAM_AHB_SEL` writer"]
4pub type W = crate::W<IRAM_DRAM_AHB_SEL_SPEC>;
5#[doc = "Field `MASK_PRO_IRAM` reader - "]
6pub type MASK_PRO_IRAM_R = crate::BitReader;
7#[doc = "Field `MASK_PRO_IRAM` writer - "]
8pub type MASK_PRO_IRAM_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `MASK_APP_IRAM` reader - "]
10pub type MASK_APP_IRAM_R = crate::BitReader;
11#[doc = "Field `MASK_APP_IRAM` writer - "]
12pub type MASK_APP_IRAM_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `MASK_PRO_DRAM` reader - "]
14pub type MASK_PRO_DRAM_R = crate::BitReader;
15#[doc = "Field `MASK_PRO_DRAM` writer - "]
16pub type MASK_PRO_DRAM_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `MASK_APP_DRAM` reader - "]
18pub type MASK_APP_DRAM_R = crate::BitReader;
19#[doc = "Field `MASK_APP_DRAM` writer - "]
20pub type MASK_APP_DRAM_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `MASK_AHB` reader - "]
22pub type MASK_AHB_R = crate::BitReader;
23#[doc = "Field `MASK_AHB` writer - "]
24pub type MASK_AHB_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `MAC_DUMP_MODE` reader - "]
26pub type MAC_DUMP_MODE_R = crate::FieldReader;
27#[doc = "Field `MAC_DUMP_MODE` writer - "]
28pub type MAC_DUMP_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29impl R {
30    #[doc = "Bit 0"]
31    #[inline(always)]
32    pub fn mask_pro_iram(&self) -> MASK_PRO_IRAM_R {
33        MASK_PRO_IRAM_R::new((self.bits & 1) != 0)
34    }
35    #[doc = "Bit 1"]
36    #[inline(always)]
37    pub fn mask_app_iram(&self) -> MASK_APP_IRAM_R {
38        MASK_APP_IRAM_R::new(((self.bits >> 1) & 1) != 0)
39    }
40    #[doc = "Bit 2"]
41    #[inline(always)]
42    pub fn mask_pro_dram(&self) -> MASK_PRO_DRAM_R {
43        MASK_PRO_DRAM_R::new(((self.bits >> 2) & 1) != 0)
44    }
45    #[doc = "Bit 3"]
46    #[inline(always)]
47    pub fn mask_app_dram(&self) -> MASK_APP_DRAM_R {
48        MASK_APP_DRAM_R::new(((self.bits >> 3) & 1) != 0)
49    }
50    #[doc = "Bit 4"]
51    #[inline(always)]
52    pub fn mask_ahb(&self) -> MASK_AHB_R {
53        MASK_AHB_R::new(((self.bits >> 4) & 1) != 0)
54    }
55    #[doc = "Bits 5:6"]
56    #[inline(always)]
57    pub fn mac_dump_mode(&self) -> MAC_DUMP_MODE_R {
58        MAC_DUMP_MODE_R::new(((self.bits >> 5) & 3) as u8)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("IRAM_DRAM_AHB_SEL")
65            .field("mask_pro_iram", &self.mask_pro_iram())
66            .field("mask_app_iram", &self.mask_app_iram())
67            .field("mask_pro_dram", &self.mask_pro_dram())
68            .field("mask_app_dram", &self.mask_app_dram())
69            .field("mask_ahb", &self.mask_ahb())
70            .field("mac_dump_mode", &self.mac_dump_mode())
71            .finish()
72    }
73}
74impl W {
75    #[doc = "Bit 0"]
76    #[inline(always)]
77    pub fn mask_pro_iram(&mut self) -> MASK_PRO_IRAM_W<IRAM_DRAM_AHB_SEL_SPEC> {
78        MASK_PRO_IRAM_W::new(self, 0)
79    }
80    #[doc = "Bit 1"]
81    #[inline(always)]
82    pub fn mask_app_iram(&mut self) -> MASK_APP_IRAM_W<IRAM_DRAM_AHB_SEL_SPEC> {
83        MASK_APP_IRAM_W::new(self, 1)
84    }
85    #[doc = "Bit 2"]
86    #[inline(always)]
87    pub fn mask_pro_dram(&mut self) -> MASK_PRO_DRAM_W<IRAM_DRAM_AHB_SEL_SPEC> {
88        MASK_PRO_DRAM_W::new(self, 2)
89    }
90    #[doc = "Bit 3"]
91    #[inline(always)]
92    pub fn mask_app_dram(&mut self) -> MASK_APP_DRAM_W<IRAM_DRAM_AHB_SEL_SPEC> {
93        MASK_APP_DRAM_W::new(self, 3)
94    }
95    #[doc = "Bit 4"]
96    #[inline(always)]
97    pub fn mask_ahb(&mut self) -> MASK_AHB_W<IRAM_DRAM_AHB_SEL_SPEC> {
98        MASK_AHB_W::new(self, 4)
99    }
100    #[doc = "Bits 5:6"]
101    #[inline(always)]
102    pub fn mac_dump_mode(&mut self) -> MAC_DUMP_MODE_W<IRAM_DRAM_AHB_SEL_SPEC> {
103        MAC_DUMP_MODE_W::new(self, 5)
104    }
105}
106#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`iram_dram_ahb_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iram_dram_ahb_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
107pub struct IRAM_DRAM_AHB_SEL_SPEC;
108impl crate::RegisterSpec for IRAM_DRAM_AHB_SEL_SPEC {
109    type Ux = u32;
110}
111#[doc = "`read()` method returns [`iram_dram_ahb_sel::R`](R) reader structure"]
112impl crate::Readable for IRAM_DRAM_AHB_SEL_SPEC {}
113#[doc = "`write(|w| ..)` method takes [`iram_dram_ahb_sel::W`](W) writer structure"]
114impl crate::Writable for IRAM_DRAM_AHB_SEL_SPEC {
115    type Safety = crate::Unsafe;
116    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
117    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
118}
119#[doc = "`reset()` method sets IRAM_DRAM_AHB_SEL to value 0"]
120impl crate::Resettable for IRAM_DRAM_AHB_SEL_SPEC {
121    const RESET_VALUE: u32 = 0;
122}
esp32/dport/iram_dram_ahb_sel.rs

esp32/dport/
iram_dram_ahb_sel.rs
