Struct esp32::emac_dma::RegisterBlock

#[repr(C)]
pub struct RegisterBlock { /* private fields */ }

Register block

Implementations

impl RegisterBlock

pub const fn dmabusmode(&self) -> &DMABUSMODE

0x00 - Bus mode configuration

pub const fn dmatxpolldemand(&self) -> &DMATXPOLLDEMAND

0x04 - When these bits are written with any value the DMA reads the current descriptor to which the Register (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host) the transmission returns to the suspend state and Bit[2] (TU) of Status Register is asserted. If the descriptor is available the transmission resumes.

pub const fn dmarxpolldemand(&self) -> &DMARXPOLLDEMAND

0x08 - When these bits are written with any value the DMA reads the current descriptor to which the Current Host Receive Descriptor Register is pointing. If that descriptor is not available (owned by the Host) the reception returns to the Suspended state and Bit[7] (RU) of Status Register is asserted. If the descriptor is available the Rx DMA returns to the active state.

pub const fn dmarxbaseaddr(&self) -> &DMARXBASEADDR

0x0c - This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB Bits[1:0] are ignored and internally taken as all-zero by the DMA. Therefore these LSB bits are read-only.

pub const fn dmatxbaseaddr(&self) -> &DMATXBASEADDR

0x10 - This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB Bits[1:0] are ignored and are internally taken as all-zero by the DMA.Therefore these LSB bits are read-only.

pub const fn dmastatus(&self) -> &DMASTATUS

0x14 - State of interrupts, errors and other events

pub const fn dmaoperation_mode(&self) -> &DMAOPERATION_MODE

0x18 - Receive and Transmit operating modes and command

pub const fn dmain_en(&self) -> &DMAIN_EN

0x1c -

pub const fn dmamissedfr(&self) -> &DMAMISSEDFR

0x20 - Missed Frame and Buffer Overflow Counter Register

pub const fn dmarintwdtimer(&self) -> &DMARINTWDTIMER

0x24 - Watchdog timer count on receive

pub const fn dmatxcurrdesc(&self) -> &DMATXCURRDESC

0x48 - The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.

pub const fn dmarxcurrdesc(&self) -> &DMARXCURRDESC

0x4c - The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.

pub const fn dmatxcurraddr_buf(&self) -> &DMATXCURRADDR_BUF

0x50 - The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.

pub const fn dmarxcurraddr_buf(&self) -> &DMARXCURRADDR_BUF

0x54 - The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.