pub type W = W<USER_SPEC>;
Expand description
Register USER
writer
Aliased Type§
struct W { /* private fields */ }
Implementations§
source§impl W
impl W
sourcepub fn doutdin(&mut self) -> DOUTDIN_W<'_, USER_SPEC>
pub fn doutdin(&mut self) -> DOUTDIN_W<'_, USER_SPEC>
Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable.
sourcepub fn cs_hold(&mut self) -> CS_HOLD_W<'_, USER_SPEC>
pub fn cs_hold(&mut self) -> CS_HOLD_W<'_, USER_SPEC>
Bit 4 - spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable.
sourcepub fn cs_setup(&mut self) -> CS_SETUP_W<'_, USER_SPEC>
pub fn cs_setup(&mut self) -> CS_SETUP_W<'_, USER_SPEC>
Bit 5 - spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable.
sourcepub fn ck_i_edge(&mut self) -> CK_I_EDGE_W<'_, USER_SPEC>
pub fn ck_i_edge(&mut self) -> CK_I_EDGE_W<'_, USER_SPEC>
Bit 6 - In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits.
sourcepub fn ck_out_edge(&mut self) -> CK_OUT_EDGE_W<'_, USER_SPEC>
pub fn ck_out_edge(&mut self) -> CK_OUT_EDGE_W<'_, USER_SPEC>
Bit 7 - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.
sourcepub fn rd_byte_order(&mut self) -> RD_BYTE_ORDER_W<'_, USER_SPEC>
pub fn rd_byte_order(&mut self) -> RD_BYTE_ORDER_W<'_, USER_SPEC>
Bit 10 - In read-data (MISO) phase 1: big-endian 0: little_endian
sourcepub fn wr_byte_order(&mut self) -> WR_BYTE_ORDER_W<'_, USER_SPEC>
pub fn wr_byte_order(&mut self) -> WR_BYTE_ORDER_W<'_, USER_SPEC>
Bit 11 - In command address write-data (MOSI) phases 1: big-endian 0: litte_endian
sourcepub fn fwrite_dual(&mut self) -> FWRITE_DUAL_W<'_, USER_SPEC>
pub fn fwrite_dual(&mut self) -> FWRITE_DUAL_W<'_, USER_SPEC>
Bit 12 - In the write operations read-data phase apply 2 signals
sourcepub fn fwrite_quad(&mut self) -> FWRITE_QUAD_W<'_, USER_SPEC>
pub fn fwrite_quad(&mut self) -> FWRITE_QUAD_W<'_, USER_SPEC>
Bit 13 - In the write operations read-data phase apply 4 signals
sourcepub fn fwrite_dio(&mut self) -> FWRITE_DIO_W<'_, USER_SPEC>
pub fn fwrite_dio(&mut self) -> FWRITE_DIO_W<'_, USER_SPEC>
Bit 14 - In the write operations address phase and read-data phase apply 2 signals.
sourcepub fn fwrite_qio(&mut self) -> FWRITE_QIO_W<'_, USER_SPEC>
pub fn fwrite_qio(&mut self) -> FWRITE_QIO_W<'_, USER_SPEC>
Bit 15 - In the write operations address phase and read-data phase apply 4 signals.
sourcepub fn sio(&mut self) -> SIO_W<'_, USER_SPEC>
pub fn sio(&mut self) -> SIO_W<'_, USER_SPEC>
Bit 16 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.
sourcepub fn usr_hold_pol(&mut self) -> USR_HOLD_POL_W<'_, USER_SPEC>
pub fn usr_hold_pol(&mut self) -> USR_HOLD_POL_W<'_, USER_SPEC>
Bit 17 - It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low
sourcepub fn usr_dout_hold(&mut self) -> USR_DOUT_HOLD_W<'_, USER_SPEC>
pub fn usr_dout_hold(&mut self) -> USR_DOUT_HOLD_W<'_, USER_SPEC>
Bit 18 - spi is hold at data out state the bit combined with spi_usr_hold_pol bit.
sourcepub fn usr_din_hold(&mut self) -> USR_DIN_HOLD_W<'_, USER_SPEC>
pub fn usr_din_hold(&mut self) -> USR_DIN_HOLD_W<'_, USER_SPEC>
Bit 19 - spi is hold at data in state the bit combined with spi_usr_hold_pol bit.
sourcepub fn usr_dummy_hold(&mut self) -> USR_DUMMY_HOLD_W<'_, USER_SPEC>
pub fn usr_dummy_hold(&mut self) -> USR_DUMMY_HOLD_W<'_, USER_SPEC>
Bit 20 - spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.
sourcepub fn usr_addr_hold(&mut self) -> USR_ADDR_HOLD_W<'_, USER_SPEC>
pub fn usr_addr_hold(&mut self) -> USR_ADDR_HOLD_W<'_, USER_SPEC>
Bit 21 - spi is hold at address state the bit combined with spi_usr_hold_pol bit.
sourcepub fn usr_cmd_hold(&mut self) -> USR_CMD_HOLD_W<'_, USER_SPEC>
pub fn usr_cmd_hold(&mut self) -> USR_CMD_HOLD_W<'_, USER_SPEC>
Bit 22 - spi is hold at command state the bit combined with spi_usr_hold_pol bit.
sourcepub fn usr_prep_hold(&mut self) -> USR_PREP_HOLD_W<'_, USER_SPEC>
pub fn usr_prep_hold(&mut self) -> USR_PREP_HOLD_W<'_, USER_SPEC>
Bit 23 - spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.
sourcepub fn usr_miso_highpart(&mut self) -> USR_MISO_HIGHPART_W<'_, USER_SPEC>
pub fn usr_miso_highpart(&mut self) -> USR_MISO_HIGHPART_W<'_, USER_SPEC>
Bit 24 - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.
sourcepub fn usr_mosi_highpart(&mut self) -> USR_MOSI_HIGHPART_W<'_, USER_SPEC>
pub fn usr_mosi_highpart(&mut self) -> USR_MOSI_HIGHPART_W<'_, USER_SPEC>
Bit 25 - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.
sourcepub fn usr_dummy_idle(&mut self) -> USR_DUMMY_IDLE_W<'_, USER_SPEC>
pub fn usr_dummy_idle(&mut self) -> USR_DUMMY_IDLE_W<'_, USER_SPEC>
Bit 26 - spi clock is disable in dummy phase when the bit is enable.
sourcepub fn usr_mosi(&mut self) -> USR_MOSI_W<'_, USER_SPEC>
pub fn usr_mosi(&mut self) -> USR_MOSI_W<'_, USER_SPEC>
Bit 27 - This bit enable the write-data phase of an operation.
sourcepub fn usr_miso(&mut self) -> USR_MISO_W<'_, USER_SPEC>
pub fn usr_miso(&mut self) -> USR_MISO_W<'_, USER_SPEC>
Bit 28 - This bit enable the read-data phase of an operation.
sourcepub fn usr_dummy(&mut self) -> USR_DUMMY_W<'_, USER_SPEC>
pub fn usr_dummy(&mut self) -> USR_DUMMY_W<'_, USER_SPEC>
Bit 29 - This bit enable the dummy phase of an operation.
sourcepub fn usr_addr(&mut self) -> USR_ADDR_W<'_, USER_SPEC>
pub fn usr_addr(&mut self) -> USR_ADDR_W<'_, USER_SPEC>
Bit 30 - This bit enable the address phase of an operation.
sourcepub fn usr_command(&mut self) -> USR_COMMAND_W<'_, USER_SPEC>
pub fn usr_command(&mut self) -> USR_COMMAND_W<'_, USER_SPEC>
Bit 31 - This bit enable the command phase of an operation.