Type Alias esp32::emac_mac::emacdebug::R

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pub type R = R<EMACDEBUG_SPEC>;
Expand description

Register EMACDEBUG reader

Aliased Type§

struct R { /* private fields */ }

Implementations§

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impl R

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pub fn macrpes(&self) -> MACRPES_R

Bit 0 - When high this bit indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state.

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pub fn macrffcs(&self) -> MACRFFCS_R

Bits 1:2 - When high this field indicates the active state of the FIFO Read and Write controllers of the MAC Receive Frame Controller Module. MACRFFCS[1] represents the status of FIFO Read controller. MACRFFCS[0] represents the status of small FIFO Write controller.

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pub fn mtlrfwcas(&self) -> MTLRFWCAS_R

Bit 4 - When high this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO.

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pub fn mtlrfrcs(&self) -> MTLRFRCS_R

Bits 5:6 - This field gives the state of the Rx FIFO read Controller: 2’b00: IDLE state.2’b01: Reading frame data.2’b10: Reading frame status (or timestamp).2’b11: Flushing the frame data and status.

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pub fn mtlrffls(&self) -> MTLRFFLS_R

Bits 8:9 - This field gives the status of the fill-level of the Rx FIFO: 2’b00: Rx FIFO Empty. 2’b01: Rx FIFO fill-level below flow-control deactivate threshold. 2’b10: Rx FIFO fill-level above flow-control activate threshold. 2’b11: Rx FIFO Full.

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pub fn mactpes(&self) -> MACTPES_R

Bit 16 - When high this bit indicates that the MAC MII transmit protocol engine is actively transmitting data and is not in the IDLE state.

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pub fn mactfcs(&self) -> MACTFCS_R

Bits 17:18 - This field indicates the state of the MAC Transmit Frame Controller module: 2’b00: IDLE state. 2’b01: Waiting for status of previous frame or IFG or backoff period to be over. 2’b10: Generating and transmitting a Pause frame (in the full-duplex mode). 2’b11: Transferring input frame for transmission.

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pub fn mactp(&self) -> MACTP_R

Bit 19 - When high this bit indicates that the MAC transmitter is in the Pause condition (in the full-duplex-mode) and hence does not schedule any frame for transmission.

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pub fn mtltfrcs(&self) -> MTLTFRCS_R

Bits 20:21 - This field indicates the state of the Tx FIFO Read Controller: 2’b00: IDLE state. 2’b01: READ state (transferring data to the MAC transmitter). 2’b10: Waiting for TxStatus from the MAC transmitter. 2’b11: Writing the received TxStatus or flushing the Tx FIFO.

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pub fn mtltfwcs(&self) -> MTLTFWCS_R

Bit 22 - When high this bit indicates that the MTL Tx FIFO Write Controller is active and is transferring data to the Tx FIFO.

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pub fn mtltfnes(&self) -> MTLTFNES_R

Bit 24 - When high this bit indicates that the MTL Tx FIFO is not empty and some data is left for Transmission.

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pub fn mtltsffs(&self) -> MTLTSFFS_R

Bit 25 - When high this bit indicates that the MTL TxStatus FIFO is full. Therefore the MTL cannot accept any more frames for transmission.