Struct esp32::spi0::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub cmd: CMD,
    pub addr: ADDR,
    pub ctrl: CTRL,
    pub ctrl1: CTRL1,
    pub rd_status: RD_STATUS,
    pub ctrl2: CTRL2,
    pub clock: CLOCK,
    pub user: USER,
    pub user1: USER1,
    pub user2: USER2,
    pub mosi_dlen: MOSI_DLEN,
    pub miso_dlen: MISO_DLEN,
    pub slv_wr_status: SLV_WR_STATUS,
    pub pin: PIN,
    pub slave: SLAVE,
    pub slave1: SLAVE1,
    pub slave2: SLAVE2,
    pub slave3: SLAVE3,
    pub slv_wrbuf_dlen: SLV_WRBUF_DLEN,
    pub slv_rdbuf_dlen: SLV_RDBUF_DLEN,
    pub cache_fctrl: CACHE_FCTRL,
    pub cache_sctrl: CACHE_SCTRL,
    pub sram_cmd: SRAM_CMD,
    pub sram_drd_cmd: SRAM_DRD_CMD,
    pub sram_dwr_cmd: SRAM_DWR_CMD,
    pub slv_rd_bit: SLV_RD_BIT,
    pub w0: W0,
    pub w1: W1,
    pub w2: W2,
    pub w3: W3,
    pub w4: W4,
    pub w5: W5,
    pub w6: W6,
    pub w7: W7,
    pub w8: W8,
    pub w9: W9,
    pub w10: W10,
    pub w11: W11,
    pub w12: W12,
    pub w13: W13,
    pub w14: W14,
    pub w15: W15,
    pub tx_crc: TX_CRC,
    pub ext0: EXT0,
    pub ext1: EXT1,
    pub ext2: EXT2,
    pub ext3: EXT3,
    pub dma_conf: DMA_CONF,
    pub dma_out_link: DMA_OUT_LINK,
    pub dma_in_link: DMA_IN_LINK,
    pub dma_status: DMA_STATUS,
    pub dma_int_ena: DMA_INT_ENA,
    pub dma_int_raw: DMA_INT_RAW,
    pub dma_int_st: DMA_INT_ST,
    pub dma_int_clr: DMA_INT_CLR,
    pub in_err_eof_des_addr: IN_ERR_EOF_DES_ADDR,
    pub in_suc_eof_des_addr: IN_SUC_EOF_DES_ADDR,
    pub inlink_dscr: INLINK_DSCR,
    pub inlink_dscr_bf0: INLINK_DSCR_BF0,
    pub inlink_dscr_bf1: INLINK_DSCR_BF1,
    pub out_eof_bfr_des_addr: OUT_EOF_BFR_DES_ADDR,
    pub out_eof_des_addr: OUT_EOF_DES_ADDR,
    pub outlink_dscr: OUTLINK_DSCR,
    pub outlink_dscr_bf0: OUTLINK_DSCR_BF0,
    pub outlink_dscr_bf1: OUTLINK_DSCR_BF1,
    pub dma_rstatus: DMA_RSTATUS,
    pub dma_tstatus: DMA_TSTATUS,
    pub date: DATE,
    /* private fields */
}

Register block

Fields

cmd: CMD

0x00 -

addr: ADDR

0x04 -

ctrl: CTRL

0x08 -

ctrl1: CTRL1

0x0c -

rd_status: RD_STATUS

0x10 -

ctrl2: CTRL2

0x14 -

clock: CLOCK

0x18 -

user: USER

0x1c -

user1: USER1

0x20 -

user2: USER2

0x24 -

mosi_dlen: MOSI_DLEN

0x28 -

miso_dlen: MISO_DLEN

0x2c -

slv_wr_status: SLV_WR_STATUS

0x30 -

pin: PIN

0x34 -

slave: SLAVE

0x38 -

slave1: SLAVE1

0x3c -

slave2: SLAVE2

0x40 -

slave3: SLAVE3

0x44 -

slv_wrbuf_dlen: SLV_WRBUF_DLEN

0x48 -

slv_rdbuf_dlen: SLV_RDBUF_DLEN

0x4c -

cache_fctrl: CACHE_FCTRL

0x50 -

cache_sctrl: CACHE_SCTRL

0x54 -

sram_cmd: SRAM_CMD

0x58 -

sram_drd_cmd: SRAM_DRD_CMD

0x5c -

sram_dwr_cmd: SRAM_DWR_CMD

0x60 -

slv_rd_bit: SLV_RD_BIT

0x64 -

w0: W0

0x80 -

w1: W1

0x84 -

w2: W2

0x88 -

w3: W3

0x8c -

w4: W4

0x90 -

w5: W5

0x94 -

w6: W6

0x98 -

w7: W7

0x9c -

w8: W8

0xa0 -

w9: W9

0xa4 -

w10: W10

0xa8 -

w11: W11

0xac -

w12: W12

0xb0 -

w13: W13

0xb4 -

w14: W14

0xb8 -

w15: W15

0xbc -

tx_crc: TX_CRC

0xc0 -

ext0: EXT0

0xf0 -

ext1: EXT1

0xf4 -

ext2: EXT2

0xf8 -

ext3: EXT3

0xfc -

dma_conf: DMA_CONF

0x100 -

dma_out_link: DMA_OUT_LINK

0x104 -

dma_in_link: DMA_IN_LINK

0x108 -

dma_status: DMA_STATUS

0x10c -

dma_int_ena: DMA_INT_ENA

0x110 -

dma_int_raw: DMA_INT_RAW

0x114 -

dma_int_st: DMA_INT_ST

0x118 -

dma_int_clr: DMA_INT_CLR

0x11c -

in_err_eof_des_addr: IN_ERR_EOF_DES_ADDR

0x120 -

in_suc_eof_des_addr: IN_SUC_EOF_DES_ADDR

0x124 -

inlink_dscr: INLINK_DSCR

0x128 -

inlink_dscr_bf0: INLINK_DSCR_BF0

0x12c -

inlink_dscr_bf1: INLINK_DSCR_BF1

0x130 -

out_eof_bfr_des_addr: OUT_EOF_BFR_DES_ADDR

0x134 -

out_eof_des_addr: OUT_EOF_DES_ADDR

0x138 -

outlink_dscr: OUTLINK_DSCR

0x13c -

outlink_dscr_bf0: OUTLINK_DSCR_BF0

0x140 -

outlink_dscr_bf1: OUTLINK_DSCR_BF1

0x144 -

dma_rstatus: DMA_RSTATUS

0x148 -

dma_tstatus: DMA_TSTATUS

0x14c -

date: DATE

0x3fc -