Struct esp32::sens::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 42 fields
    pub sar_read_ctrl: SAR_READ_CTRL,
    pub sar_read_status1: SAR_READ_STATUS1,
    pub sar_meas_wait1: SAR_MEAS_WAIT1,
    pub sar_meas_wait2: SAR_MEAS_WAIT2,
    pub sar_meas_ctrl: SAR_MEAS_CTRL,
    pub sar_read_status2: SAR_READ_STATUS2,
    pub ulp_cp_sleep_cyc0: ULP_CP_SLEEP_CYC0,
    pub ulp_cp_sleep_cyc1: ULP_CP_SLEEP_CYC1,
    pub ulp_cp_sleep_cyc2: ULP_CP_SLEEP_CYC2,
    pub ulp_cp_sleep_cyc3: ULP_CP_SLEEP_CYC3,
    pub ulp_cp_sleep_cyc4: ULP_CP_SLEEP_CYC4,
    pub sar_start_force: SAR_START_FORCE,
    pub sar_mem_wr_ctrl: SAR_MEM_WR_CTRL,
    pub sar_atten1: SAR_ATTEN1,
    pub sar_atten2: SAR_ATTEN2,
    pub sar_slave_addr1: SAR_SLAVE_ADDR1,
    pub sar_slave_addr2: SAR_SLAVE_ADDR2,
    pub sar_slave_addr3: SAR_SLAVE_ADDR3,
    pub sar_slave_addr4: SAR_SLAVE_ADDR4,
    pub sar_tsens_ctrl: SAR_TSENS_CTRL,
    pub sar_i2c_ctrl: SAR_I2C_CTRL,
    pub sar_meas_start1: SAR_MEAS_START1,
    pub sar_touch_ctrl1: SAR_TOUCH_CTRL1,
    pub sar_touch_thres1: SAR_TOUCH_THRES1,
    pub sar_touch_thres2: SAR_TOUCH_THRES2,
    pub sar_touch_thres3: SAR_TOUCH_THRES3,
    pub sar_touch_thres4: SAR_TOUCH_THRES4,
    pub sar_touch_thres5: SAR_TOUCH_THRES5,
    pub sar_touch_out1: SAR_TOUCH_OUT1,
    pub sar_touch_out2: SAR_TOUCH_OUT2,
    pub sar_touch_out3: SAR_TOUCH_OUT3,
    pub sar_touch_out4: SAR_TOUCH_OUT4,
    pub sar_touch_out5: SAR_TOUCH_OUT5,
    pub sar_touch_ctrl2: SAR_TOUCH_CTRL2,
    pub sar_touch_enable: SAR_TOUCH_ENABLE,
    pub sar_read_ctrl2: SAR_READ_CTRL2,
    pub sar_meas_start2: SAR_MEAS_START2,
    pub sar_dac_ctrl1: SAR_DAC_CTRL1,
    pub sar_dac_ctrl2: SAR_DAC_CTRL2,
    pub sar_meas_ctrl2: SAR_MEAS_CTRL2,
    pub sar_nouse: SAR_NOUSE,
    pub sardate: SARDATE,
    /* private fields */

}
Expand description

Register block

Fields§

§sar_read_ctrl: SAR_READ_CTRL

0x00 -

§sar_read_status1: SAR_READ_STATUS1

0x04 -

§sar_meas_wait1: SAR_MEAS_WAIT1

0x08 -

§sar_meas_wait2: SAR_MEAS_WAIT2

0x0c -

§sar_meas_ctrl: SAR_MEAS_CTRL

0x10 -

§sar_read_status2: SAR_READ_STATUS2

0x14 -

§ulp_cp_sleep_cyc0: ULP_CP_SLEEP_CYC0

0x18 -

§ulp_cp_sleep_cyc1: ULP_CP_SLEEP_CYC1

0x1c -

§ulp_cp_sleep_cyc2: ULP_CP_SLEEP_CYC2

0x20 -

§ulp_cp_sleep_cyc3: ULP_CP_SLEEP_CYC3

0x24 -

§ulp_cp_sleep_cyc4: ULP_CP_SLEEP_CYC4

0x28 -

§sar_start_force: SAR_START_FORCE

0x2c -

§sar_mem_wr_ctrl: SAR_MEM_WR_CTRL

0x30 -

§sar_atten1: SAR_ATTEN1

0x34 -

§sar_atten2: SAR_ATTEN2

0x38 -

§sar_slave_addr1: SAR_SLAVE_ADDR1

0x3c -

§sar_slave_addr2: SAR_SLAVE_ADDR2

0x40 -

§sar_slave_addr3: SAR_SLAVE_ADDR3

0x44 -

§sar_slave_addr4: SAR_SLAVE_ADDR4

0x48 -

§sar_tsens_ctrl: SAR_TSENS_CTRL

0x4c -

§sar_i2c_ctrl: SAR_I2C_CTRL

0x50 -

§sar_meas_start1: SAR_MEAS_START1

0x54 -

§sar_touch_ctrl1: SAR_TOUCH_CTRL1

0x58 -

§sar_touch_thres1: SAR_TOUCH_THRES1

0x5c -

§sar_touch_thres2: SAR_TOUCH_THRES2

0x60 -

§sar_touch_thres3: SAR_TOUCH_THRES3

0x64 -

§sar_touch_thres4: SAR_TOUCH_THRES4

0x68 -

§sar_touch_thres5: SAR_TOUCH_THRES5

0x6c -

§sar_touch_out1: SAR_TOUCH_OUT1

0x70 -

§sar_touch_out2: SAR_TOUCH_OUT2

0x74 -

§sar_touch_out3: SAR_TOUCH_OUT3

0x78 -

§sar_touch_out4: SAR_TOUCH_OUT4

0x7c -

§sar_touch_out5: SAR_TOUCH_OUT5

0x80 -

§sar_touch_ctrl2: SAR_TOUCH_CTRL2

0x84 -

§sar_touch_enable: SAR_TOUCH_ENABLE

0x8c -

§sar_read_ctrl2: SAR_READ_CTRL2

0x90 -

§sar_meas_start2: SAR_MEAS_START2

0x94 -

§sar_dac_ctrl1: SAR_DAC_CTRL1

0x98 -

§sar_dac_ctrl2: SAR_DAC_CTRL2

0x9c -

§sar_meas_ctrl2: SAR_MEAS_CTRL2

0xa0 -

§sar_nouse: SAR_NOUSE

0xf8 -

§sardate: SARDATE

0xfc -

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