Struct esp32::dport::cache_ia_int_en::W

pub struct W(_);

Register CACHE_IA_INT_EN writer

Implementations

impl W

pub fn cache_ia_int_en(&mut self) -> CACHE_IA_INT_EN_W<'_, 0>

Bits 0:27 - Interrupt enable bits for various invalid cache access reasons

pub fn cache_ia_int_app_drom0(&mut self) -> CACHE_IA_INT_APP_DROM0_W<'_, 0>

Bit 0 - APP CPU invalid access to DROM0 when cache is disabled

pub fn cache_ia_int_app_iram0(&mut self) -> CACHE_IA_INT_APP_IRAM0_W<'_, 1>

Bit 1 - APP CPU invalid access to IRAM0 when cache is disabled

pub fn cache_ia_int_app_iram1(&mut self) -> CACHE_IA_INT_APP_IRAM1_W<'_, 2>

Bit 2 - APP CPU invalid access to IRAM1 when cache is disabled

pub fn cache_ia_int_app_irom0(&mut self) -> CACHE_IA_INT_APP_IROM0_W<'_, 3>

Bit 3 - APP CPU invalid access to IROM0 when cache is disabled

pub fn cache_ia_int_app_dram1(&mut self) -> CACHE_IA_INT_APP_DRAM1_W<'_, 4>

Bit 4 - APP CPU invalid access to DRAM1 when cache is disabled

pub fn cache_ia_int_app_opposite( &mut self ) -> CACHE_IA_INT_APP_OPPOSITE_W<'_, 5>

Bit 5 - APP CPU invalid access to APP CPU cache when cache disabled

pub fn cache_ia_int_pro_drom0(&mut self) -> CACHE_IA_INT_PRO_DROM0_W<'_, 14>

Bit 14 - PRO CPU invalid access to DROM0 when cache is disabled

pub fn cache_ia_int_pro_iram0(&mut self) -> CACHE_IA_INT_PRO_IRAM0_W<'_, 15>

Bit 15 - PRO CPU invalid access to IRAM0 when cache is disabled

pub fn cache_ia_int_pro_iram1(&mut self) -> CACHE_IA_INT_PRO_IRAM1_W<'_, 16>

Bit 16 - PRO CPU invalid access to IRAM1 when cache is disabled

pub fn cache_ia_int_pro_irom0(&mut self) -> CACHE_IA_INT_PRO_IROM0_W<'_, 17>

Bit 17 - PRO CPU invalid access to IROM0 when cache is disabled

pub fn cache_ia_int_pro_dram1(&mut self) -> CACHE_IA_INT_PRO_DRAM1_W<'_, 18>

Bit 18 - PRO CPU invalid access to DRAM1 when cache is disabled

pub fn cache_ia_int_pro_opposite( &mut self ) -> CACHE_IA_INT_PRO_OPPOSITE_W<'_, 19>

Bit 19 - PRO CPU invalid access to APP CPU cache when cache disabled

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<CACHE_IA_INT_EN_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CACHE_IA_INT_EN_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<CACHE_IA_INT_EN_SPEC>> for W

fn from(writer: W<CACHE_IA_INT_EN_SPEC>) -> Self

Converts to this type from the input type.