Struct esp32::spi0::cache_fctrl::W

pub struct W(_);

Register CACHE_FCTRL writer

Implementations

impl W

pub fn cache_req_en(&mut self) -> CACHE_REQ_EN_W<'_, 0>

Bit 0 - For SPI0 Cache access enable 1: enable 0:disable.

pub fn cache_usr_cmd_4byte(&mut self) -> CACHE_USR_CMD_4BYTE_W<'_, 1>

Bit 1 - For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.

pub fn cache_flash_usr_cmd(&mut self) -> CACHE_FLASH_USR_CMD_W<'_, 2>

Bit 2 - For SPI0 cache read flash for user define command 1: enable 0:disable.

pub fn cache_flash_pes_en(&mut self) -> CACHE_FLASH_PES_EN_W<'_, 3>

Bit 3 - For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<CACHE_FCTRL_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CACHE_FCTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<CACHE_FCTRL_SPEC>> for W

fn from(writer: W<CACHE_FCTRL_SPEC>) -> Self

Converts to this type from the input type.