Struct esp32::dport::cache_ia_int_en::R
source · pub struct R(_);Expand description
Register CACHE_IA_INT_EN reader
Implementations§
source§impl R
impl R
sourcepub fn cache_ia_int_en(&self) -> CACHE_IA_INT_EN_R
pub fn cache_ia_int_en(&self) -> CACHE_IA_INT_EN_R
Bits 0:27 - Interrupt enable bits for various invalid cache access reasons
sourcepub fn cache_ia_int_app_drom0(&self) -> CACHE_IA_INT_APP_DROM0_R
pub fn cache_ia_int_app_drom0(&self) -> CACHE_IA_INT_APP_DROM0_R
Bit 0 - APP CPU invalid access to DROM0 when cache is disabled
sourcepub fn cache_ia_int_app_iram0(&self) -> CACHE_IA_INT_APP_IRAM0_R
pub fn cache_ia_int_app_iram0(&self) -> CACHE_IA_INT_APP_IRAM0_R
Bit 1 - APP CPU invalid access to IRAM0 when cache is disabled
sourcepub fn cache_ia_int_app_iram1(&self) -> CACHE_IA_INT_APP_IRAM1_R
pub fn cache_ia_int_app_iram1(&self) -> CACHE_IA_INT_APP_IRAM1_R
Bit 2 - APP CPU invalid access to IRAM1 when cache is disabled
sourcepub fn cache_ia_int_app_irom0(&self) -> CACHE_IA_INT_APP_IROM0_R
pub fn cache_ia_int_app_irom0(&self) -> CACHE_IA_INT_APP_IROM0_R
Bit 3 - APP CPU invalid access to IROM0 when cache is disabled
sourcepub fn cache_ia_int_app_dram1(&self) -> CACHE_IA_INT_APP_DRAM1_R
pub fn cache_ia_int_app_dram1(&self) -> CACHE_IA_INT_APP_DRAM1_R
Bit 4 - APP CPU invalid access to DRAM1 when cache is disabled
sourcepub fn cache_ia_int_app_opposite(&self) -> CACHE_IA_INT_APP_OPPOSITE_R
pub fn cache_ia_int_app_opposite(&self) -> CACHE_IA_INT_APP_OPPOSITE_R
Bit 5 - APP CPU invalid access to APP CPU cache when cache disabled
sourcepub fn cache_ia_int_pro_drom0(&self) -> CACHE_IA_INT_PRO_DROM0_R
pub fn cache_ia_int_pro_drom0(&self) -> CACHE_IA_INT_PRO_DROM0_R
Bit 14 - PRO CPU invalid access to DROM0 when cache is disabled
sourcepub fn cache_ia_int_pro_iram0(&self) -> CACHE_IA_INT_PRO_IRAM0_R
pub fn cache_ia_int_pro_iram0(&self) -> CACHE_IA_INT_PRO_IRAM0_R
Bit 15 - PRO CPU invalid access to IRAM0 when cache is disabled
sourcepub fn cache_ia_int_pro_iram1(&self) -> CACHE_IA_INT_PRO_IRAM1_R
pub fn cache_ia_int_pro_iram1(&self) -> CACHE_IA_INT_PRO_IRAM1_R
Bit 16 - PRO CPU invalid access to IRAM1 when cache is disabled
sourcepub fn cache_ia_int_pro_irom0(&self) -> CACHE_IA_INT_PRO_IROM0_R
pub fn cache_ia_int_pro_irom0(&self) -> CACHE_IA_INT_PRO_IROM0_R
Bit 17 - PRO CPU invalid access to IROM0 when cache is disabled
sourcepub fn cache_ia_int_pro_dram1(&self) -> CACHE_IA_INT_PRO_DRAM1_R
pub fn cache_ia_int_pro_dram1(&self) -> CACHE_IA_INT_PRO_DRAM1_R
Bit 18 - PRO CPU invalid access to DRAM1 when cache is disabled
sourcepub fn cache_ia_int_pro_opposite(&self) -> CACHE_IA_INT_PRO_OPPOSITE_R
pub fn cache_ia_int_pro_opposite(&self) -> CACHE_IA_INT_PRO_OPPOSITE_R
Bit 19 - PRO CPU invalid access to APP CPU cache when cache disabled