Struct esp32::rmt::int_st::R

pub struct R(_);

Register INT_ST reader

Implementations

impl R

pub unsafe fn ch_tx_end_int_st(&self, n: u8) -> CH_TX_END_INT_ST_R

The interrupt state bit for channel [0-7]’s mt_ch[0-7]_tx_end_int_raw when mt_ch[0-7]_tx_end_int_ena is set to [0-7].

pub fn ch0_tx_end_int_st(&self) -> CH_TX_END_INT_ST_R

Bit 0 - The interrupt state bit for channel 0’s mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.

pub fn ch1_tx_end_int_st(&self) -> CH_TX_END_INT_ST_R

Bit 3 - The interrupt state bit for channel 1’s mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.

pub fn ch2_tx_end_int_st(&self) -> CH_TX_END_INT_ST_R

Bit 6 - The interrupt state bit for channel 2’s mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 2.

pub fn ch3_tx_end_int_st(&self) -> CH_TX_END_INT_ST_R

Bit 9 - The interrupt state bit for channel 3’s mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 3.

pub fn ch4_tx_end_int_st(&self) -> CH_TX_END_INT_ST_R

Bit 12 - The interrupt state bit for channel 4’s mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 4.

pub fn ch5_tx_end_int_st(&self) -> CH_TX_END_INT_ST_R

Bit 15 - The interrupt state bit for channel 5’s mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 5.

pub fn ch6_tx_end_int_st(&self) -> CH_TX_END_INT_ST_R

Bit 18 - The interrupt state bit for channel 6’s mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 6.

pub fn ch7_tx_end_int_st(&self) -> CH_TX_END_INT_ST_R

Bit 21 - The interrupt state bit for channel 7’s mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 7.

pub unsafe fn ch_rx_end_int_st(&self, n: u8) -> CH_RX_END_INT_ST_R

The interrupt state bit for channel [0-7]’s rmt_ch[0-7]_rx_end_int_raw when rmt_ch[0-7]_rx_end_int_ena is set to [0-7].

pub fn ch0_rx_end_int_st(&self) -> CH_RX_END_INT_ST_R

Bit 1 - The interrupt state bit for channel 0’s rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0.

pub fn ch1_rx_end_int_st(&self) -> CH_RX_END_INT_ST_R

Bit 4 - The interrupt state bit for channel 1’s rmt_ch1_rx_end_int_raw when rmt_ch1_rx_end_int_ena is set to 1.

pub fn ch2_rx_end_int_st(&self) -> CH_RX_END_INT_ST_R

Bit 7 - The interrupt state bit for channel 2’s rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena is set to 2.

pub fn ch3_rx_end_int_st(&self) -> CH_RX_END_INT_ST_R

Bit 10 - The interrupt state bit for channel 3’s rmt_ch3_rx_end_int_raw when rmt_ch3_rx_end_int_ena is set to 3.

pub fn ch4_rx_end_int_st(&self) -> CH_RX_END_INT_ST_R

Bit 13 - The interrupt state bit for channel 4’s rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 4.

pub fn ch5_rx_end_int_st(&self) -> CH_RX_END_INT_ST_R

Bit 16 - The interrupt state bit for channel 5’s rmt_ch5_rx_end_int_raw when rmt_ch5_rx_end_int_ena is set to 5.

pub fn ch6_rx_end_int_st(&self) -> CH_RX_END_INT_ST_R

Bit 19 - The interrupt state bit for channel 6’s rmt_ch6_rx_end_int_raw when rmt_ch6_rx_end_int_ena is set to 6.

pub fn ch7_rx_end_int_st(&self) -> CH_RX_END_INT_ST_R

Bit 22 - The interrupt state bit for channel 7’s rmt_ch7_rx_end_int_raw when rmt_ch7_rx_end_int_ena is set to 7.

pub unsafe fn ch_err_int_st(&self, n: u8) -> CH_ERR_INT_ST_R

The interrupt state bit for channel [0-7]’s rmt_ch[0-7]_err_int_raw when rmt_ch[0-7]_err_int_ena is set to [0-7].

pub fn ch0_err_int_st(&self) -> CH_ERR_INT_ST_R

Bit 2 - The interrupt state bit for channel 0’s rmt_ch0_err_int_raw when rmt_ch0_err_int_ena is set to 0.

pub fn ch1_err_int_st(&self) -> CH_ERR_INT_ST_R

Bit 5 - The interrupt state bit for channel 1’s rmt_ch1_err_int_raw when rmt_ch1_err_int_ena is set to 1.

pub fn ch2_err_int_st(&self) -> CH_ERR_INT_ST_R

Bit 8 - The interrupt state bit for channel 2’s rmt_ch2_err_int_raw when rmt_ch2_err_int_ena is set to 2.

pub fn ch3_err_int_st(&self) -> CH_ERR_INT_ST_R

Bit 11 - The interrupt state bit for channel 3’s rmt_ch3_err_int_raw when rmt_ch3_err_int_ena is set to 3.

pub fn ch4_err_int_st(&self) -> CH_ERR_INT_ST_R

Bit 14 - The interrupt state bit for channel 4’s rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is set to 4.

pub fn ch5_err_int_st(&self) -> CH_ERR_INT_ST_R

Bit 17 - The interrupt state bit for channel 5’s rmt_ch5_err_int_raw when rmt_ch5_err_int_ena is set to 5.

pub fn ch6_err_int_st(&self) -> CH_ERR_INT_ST_R

Bit 20 - The interrupt state bit for channel 6’s rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 6.

pub fn ch7_err_int_st(&self) -> CH_ERR_INT_ST_R

Bit 23 - The interrupt state bit for channel 7’s rmt_ch7_err_int_raw when rmt_ch7_err_int_ena is set to 7.

pub unsafe fn ch_tx_thr_event_int_st(&self, n: u8) -> CH_TX_THR_EVENT_INT_ST_R

The interrupt state bit for channel [0-7]’s rmt_ch[0-7]_tx_thr_event_int_raw when mt_ch[0-7]_tx_thr_event_int_ena is set to 1.

pub fn ch0_tx_thr_event_int_st(&self) -> CH_TX_THR_EVENT_INT_ST_R

Bit 24 - The interrupt state bit for channel 0’s rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.

pub fn ch1_tx_thr_event_int_st(&self) -> CH_TX_THR_EVENT_INT_ST_R

Bit 25 - The interrupt state bit for channel 1’s rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.

pub fn ch2_tx_thr_event_int_st(&self) -> CH_TX_THR_EVENT_INT_ST_R

Bit 26 - The interrupt state bit for channel 2’s rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.

pub fn ch3_tx_thr_event_int_st(&self) -> CH_TX_THR_EVENT_INT_ST_R

Bit 27 - The interrupt state bit for channel 3’s rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.

pub fn ch4_tx_thr_event_int_st(&self) -> CH_TX_THR_EVENT_INT_ST_R

Bit 28 - The interrupt state bit for channel 4’s rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.

pub fn ch5_tx_thr_event_int_st(&self) -> CH_TX_THR_EVENT_INT_ST_R

Bit 29 - The interrupt state bit for channel 5’s rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.

pub fn ch6_tx_thr_event_int_st(&self) -> CH_TX_THR_EVENT_INT_ST_R

Bit 30 - The interrupt state bit for channel 6’s rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.

pub fn ch7_tx_thr_event_int_st(&self) -> CH_TX_THR_EVENT_INT_ST_R

Bit 31 - The interrupt state bit for channel 7’s rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.

Methods from Deref<Target = R<INT_ST_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<INT_ST_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<INT_ST_SPEC>> for R

fn from(reader: R<INT_ST_SPEC>) -> Self

Converts to this type from the input type.