Struct esp32::apb_ctrl::apb_saradc_ctrl::R

pub struct R(_);

Register APB_SARADC_CTRL reader

Implementations

impl R

pub fn saradc_start_force(&self) -> SARADC_START_FORCE_R

Bit 0

pub fn saradc_start(&self) -> SARADC_START_R

Bit 1

pub fn saradc_sar2_mux(&self) -> SARADC_SAR2_MUX_R

Bit 2 - 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL

pub fn saradc_work_mode(&self) -> SARADC_WORK_MODE_R

Bits 3:4 - 0: single mode 1: double mode 2: alternate mode

pub fn saradc_sar_sel(&self) -> SARADC_SAR_SEL_R

Bit 5 - 0: SAR1 1: SAR2 only work for single SAR mode

pub fn saradc_sar_clk_gated(&self) -> SARADC_SAR_CLK_GATED_R

Bit 6

pub fn saradc_sar_clk_div(&self) -> SARADC_SAR_CLK_DIV_R

Bits 7:14 - SAR clock divider

pub fn saradc_sar1_patt_len(&self) -> SARADC_SAR1_PATT_LEN_R

Bits 15:18 - 0 ~ 15 means length 1 ~ 16

pub fn saradc_sar2_patt_len(&self) -> SARADC_SAR2_PATT_LEN_R

Bits 19:22 - 0 ~ 15 means length 1 ~ 16

pub fn saradc_sar1_patt_p_clear(&self) -> SARADC_SAR1_PATT_P_CLEAR_R

Bit 23 - clear the pointer of pattern table for DIG ADC1 CTRL

pub fn saradc_sar2_patt_p_clear(&self) -> SARADC_SAR2_PATT_P_CLEAR_R

Bit 24 - clear the pointer of pattern table for DIG ADC2 CTRL

pub fn saradc_data_sar_sel(&self) -> SARADC_DATA_SAR_SEL_R

Bit 25 - 1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.

pub fn saradc_data_to_i2s(&self) -> SARADC_DATA_TO_I2S_R

Bit 26 - 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix

Methods from Deref<Target = R<APB_SARADC_CTRL_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<APB_SARADC_CTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<APB_SARADC_CTRL_SPEC>> for R

fn from(reader: R<APB_SARADC_CTRL_SPEC>) -> Self

Converts to this type from the input type.