pub struct R(_);
Expand description
Register CLK_CONF
reader
Implementations§
source§impl R
impl R
sourcepub fn ck8m_div(&self) -> CK8M_DIV_R
pub fn ck8m_div(&self) -> CK8M_DIV_R
Bits 4:5 - CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.
sourcepub fn enb_ck8m(&self) -> ENB_CK8M_R
pub fn enb_ck8m(&self) -> ENB_CK8M_R
Bit 6 - disable CK8M and CK8M_D256_OUT
sourcepub fn enb_ck8m_div(&self) -> ENB_CK8M_DIV_R
pub fn enb_ck8m_div(&self) -> ENB_CK8M_DIV_R
Bit 7 - 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256
sourcepub fn dig_xtal32k_en(&self) -> DIG_XTAL32K_EN_R
pub fn dig_xtal32k_en(&self) -> DIG_XTAL32K_EN_R
Bit 8 - enable CK_XTAL_32K for digital core (no relationship with RTC core)
sourcepub fn dig_clk8m_d256_en(&self) -> DIG_CLK8M_D256_EN_R
pub fn dig_clk8m_d256_en(&self) -> DIG_CLK8M_D256_EN_R
Bit 9 - enable CK8M_D256_OUT for digital core (no relationship with RTC core)
sourcepub fn dig_clk8m_en(&self) -> DIG_CLK8M_EN_R
pub fn dig_clk8m_en(&self) -> DIG_CLK8M_EN_R
Bit 10 - enable CK8M for digital core (no relationship with RTC core)
sourcepub fn ck8m_dfreq_force(&self) -> CK8M_DFREQ_FORCE_R
pub fn ck8m_dfreq_force(&self) -> CK8M_DFREQ_FORCE_R
Bit 11
sourcepub fn ck8m_div_sel(&self) -> CK8M_DIV_SEL_R
pub fn ck8m_div_sel(&self) -> CK8M_DIV_SEL_R
Bits 12:14 - divider = reg_ck8m_div_sel + 1
sourcepub fn xtal_force_nogating(&self) -> XTAL_FORCE_NOGATING_R
pub fn xtal_force_nogating(&self) -> XTAL_FORCE_NOGATING_R
Bit 15 - XTAL force no gating during sleep
sourcepub fn ck8m_force_nogating(&self) -> CK8M_FORCE_NOGATING_R
pub fn ck8m_force_nogating(&self) -> CK8M_FORCE_NOGATING_R
Bit 16 - CK8M force no gating during sleep
sourcepub fn ck8m_dfreq(&self) -> CK8M_DFREQ_R
pub fn ck8m_dfreq(&self) -> CK8M_DFREQ_R
Bits 17:24 - CK8M_DFREQ
sourcepub fn ck8m_force_pd(&self) -> CK8M_FORCE_PD_R
pub fn ck8m_force_pd(&self) -> CK8M_FORCE_PD_R
Bit 25 - CK8M force power down
sourcepub fn ck8m_force_pu(&self) -> CK8M_FORCE_PU_R
pub fn ck8m_force_pu(&self) -> CK8M_FORCE_PU_R
Bit 26 - CK8M force power up
sourcepub fn soc_clk_sel(&self) -> SOC_CLK_SEL_R
pub fn soc_clk_sel(&self) -> SOC_CLK_SEL_R
Bits 27:28 - SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL
sourcepub fn fast_clk_rtc_sel(&self) -> FAST_CLK_RTC_SEL_R
pub fn fast_clk_rtc_sel(&self) -> FAST_CLK_RTC_SEL_R
Bit 29 - fast_clk_rtc sel. 0: XTAL div 4 1: CK8M
sourcepub fn ana_clk_rtc_sel(&self) -> ANA_CLK_RTC_SEL_R
pub fn ana_clk_rtc_sel(&self) -> ANA_CLK_RTC_SEL_R
Bits 30:31 - slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT