Struct esp32::spi0::ctrl2::W

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pub struct W(_);

Expand description

Register CTRL2 writer

Implementations

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impl W

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pub fn setup_time(&mut self) -> SETUP_TIME_W<'_, 0>

Bits 0:3 - (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit.

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pub fn hold_time(&mut self) -> HOLD_TIME_W<'_, 4>

Bits 4:7 - delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.

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pub fn ck_out_low_mode(&mut self) -> CK_OUT_LOW_MODE_W<'_, 8>

Bits 8:11 - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.

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pub fn ck_out_high_mode(&mut self) -> CK_OUT_HIGH_MODE_W<'_, 12>

Bits 12:15 - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.

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pub fn miso_delay_mode(&mut self) -> MISO_DELAY_MODE_W<'_, 16>

Bits 16:17 - MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle

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pub fn miso_delay_num(&mut self) -> MISO_DELAY_NUM_W<'_, 18>

Bits 18:20 - MISO signals are delayed by system clock cycles

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pub fn mosi_delay_mode(&mut self) -> MOSI_DELAY_MODE_W<'_, 21>

Bits 21:22 - MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle

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pub fn mosi_delay_num(&mut self) -> MOSI_DELAY_NUM_W<'_, 23>

Bits 23:25 - MOSI signals are delayed by system clock cycles

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pub fn cs_delay_mode(&mut self) -> CS_DELAY_MODE_W<'_, 26>

Bits 26:27 - spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle

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