Struct esp32::sdmmc::clk_edge_sel::W

pub struct W(_);

Register CLK_EDGE_SEL writer

Implementations

impl W

pub fn cclkin_edge_drv_sel(&mut self) -> CCLKIN_EDGE_DRV_SEL_W<'_, 0>

Bits 0:2 - It’s used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270.

pub fn cclkin_edge_sam_sel(&mut self) -> CCLKIN_EDGE_SAM_SEL_W<'_, 3>

Bits 3:5 - It’s used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270.

pub fn cclkin_edge_slf_sel(&mut self) -> CCLKIN_EDGE_SLF_SEL_W<'_, 6>

Bits 6:8 - It’s used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270.

pub fn ccllkin_edge_h(&mut self) -> CCLLKIN_EDGE_H_W<'_, 9>

Bits 9:12 - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L.

pub fn ccllkin_edge_l(&mut self) -> CCLLKIN_EDGE_L_W<'_, 13>

Bits 13:16 - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H.

pub fn ccllkin_edge_n(&mut self) -> CCLLKIN_EDGE_N_W<'_, 17>

Bits 17:20 - The value should be equal to CCLKIN_EDGE_L.

pub fn esdio_mode(&mut self) -> ESDIO_MODE_W<'_, 21>

Bit 21 - Enable esdio mode.

pub fn esd_mode(&mut self) -> ESD_MODE_W<'_, 22>

Bit 22 - Enable esd mode.

pub fn cclk_en(&mut self) -> CCLK_EN_W<'_, 23>

Bit 23 - Sdio clock enable

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<CLK_EDGE_SEL_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<CLK_EDGE_SEL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<CLK_EDGE_SEL_SPEC>> for W

fn from(writer: W<CLK_EDGE_SEL_SPEC>) -> Self

Converts to this type from the input type.