Struct esp32::slc::RegisterBlock
source · [−]#[repr(C)]pub struct RegisterBlock {Show 83 fields
pub conf0: Reg<CONF0_SPEC>,
pub _0int_raw: Reg<_0INT_RAW_SPEC>,
pub _0int_st: Reg<_0INT_ST_SPEC>,
pub _0int_ena: Reg<_0INT_ENA_SPEC>,
pub _0int_clr: Reg<_0INT_CLR_SPEC>,
pub _1int_raw: Reg<_1INT_RAW_SPEC>,
pub _1int_st: Reg<_1INT_ST_SPEC>,
pub _1int_ena: Reg<_1INT_ENA_SPEC>,
pub _1int_clr: Reg<_1INT_CLR_SPEC>,
pub rx_status: Reg<RX_STATUS_SPEC>,
pub _0rxfifo_push: Reg<_0RXFIFO_PUSH_SPEC>,
pub _1rxfifo_push: Reg<_1RXFIFO_PUSH_SPEC>,
pub tx_status: Reg<TX_STATUS_SPEC>,
pub _0txfifo_pop: Reg<_0TXFIFO_POP_SPEC>,
pub _1txfifo_pop: Reg<_1TXFIFO_POP_SPEC>,
pub _0rx_link: Reg<_0RX_LINK_SPEC>,
pub _0tx_link: Reg<_0TX_LINK_SPEC>,
pub _1rx_link: Reg<_1RX_LINK_SPEC>,
pub _1tx_link: Reg<_1TX_LINK_SPEC>,
pub intvec_tohost: Reg<INTVEC_TOHOST_SPEC>,
pub _0token0: Reg<_0TOKEN0_SPEC>,
pub _0token1: Reg<_0TOKEN1_SPEC>,
pub _1token0: Reg<_1TOKEN0_SPEC>,
pub _1token1: Reg<_1TOKEN1_SPEC>,
pub conf1: Reg<CONF1_SPEC>,
pub _0_state0: Reg<_0_STATE0_SPEC>,
pub _0_state1: Reg<_0_STATE1_SPEC>,
pub _1_state0: Reg<_1_STATE0_SPEC>,
pub _1_state1: Reg<_1_STATE1_SPEC>,
pub bridge_conf: Reg<BRIDGE_CONF_SPEC>,
pub _0_to_eof_des_addr: Reg<_0_TO_EOF_DES_ADDR_SPEC>,
pub _0_tx_eof_des_addr: Reg<_0_TX_EOF_DES_ADDR_SPEC>,
pub _0_to_eof_bfr_des_addr: Reg<_0_TO_EOF_BFR_DES_ADDR_SPEC>,
pub _1_to_eof_des_addr: Reg<_1_TO_EOF_DES_ADDR_SPEC>,
pub _1_tx_eof_des_addr: Reg<_1_TX_EOF_DES_ADDR_SPEC>,
pub _1_to_eof_bfr_des_addr: Reg<_1_TO_EOF_BFR_DES_ADDR_SPEC>,
pub ahb_test: Reg<AHB_TEST_SPEC>,
pub sdio_st: Reg<SDIO_ST_SPEC>,
pub rx_dscr_conf: Reg<RX_DSCR_CONF_SPEC>,
pub _0_txlink_dscr: Reg<_0_TXLINK_DSCR_SPEC>,
pub _0_txlink_dscr_bf0: Reg<_0_TXLINK_DSCR_BF0_SPEC>,
pub _0_txlink_dscr_bf1: Reg<_0_TXLINK_DSCR_BF1_SPEC>,
pub _0_rxlink_dscr: Reg<_0_RXLINK_DSCR_SPEC>,
pub _0_rxlink_dscr_bf0: Reg<_0_RXLINK_DSCR_BF0_SPEC>,
pub _0_rxlink_dscr_bf1: Reg<_0_RXLINK_DSCR_BF1_SPEC>,
pub _1_txlink_dscr: Reg<_1_TXLINK_DSCR_SPEC>,
pub _1_txlink_dscr_bf0: Reg<_1_TXLINK_DSCR_BF0_SPEC>,
pub _1_txlink_dscr_bf1: Reg<_1_TXLINK_DSCR_BF1_SPEC>,
pub _1_rxlink_dscr: Reg<_1_RXLINK_DSCR_SPEC>,
pub _1_rxlink_dscr_bf0: Reg<_1_RXLINK_DSCR_BF0_SPEC>,
pub _1_rxlink_dscr_bf1: Reg<_1_RXLINK_DSCR_BF1_SPEC>,
pub _0_tx_erreof_des_addr: Reg<_0_TX_ERREOF_DES_ADDR_SPEC>,
pub _1_tx_erreof_des_addr: Reg<_1_TX_ERREOF_DES_ADDR_SPEC>,
pub token_lat: Reg<TOKEN_LAT_SPEC>,
pub tx_dscr_conf: Reg<TX_DSCR_CONF_SPEC>,
pub cmd_infor0: Reg<CMD_INFOR0_SPEC>,
pub cmd_infor1: Reg<CMD_INFOR1_SPEC>,
pub _0_len_conf: Reg<_0_LEN_CONF_SPEC>,
pub _0_length: Reg<_0_LENGTH_SPEC>,
pub _0_txpkt_h_dscr: Reg<_0_TXPKT_H_DSCR_SPEC>,
pub _0_txpkt_e_dscr: Reg<_0_TXPKT_E_DSCR_SPEC>,
pub _0_rxpkt_h_dscr: Reg<_0_RXPKT_H_DSCR_SPEC>,
pub _0_rxpkt_e_dscr: Reg<_0_RXPKT_E_DSCR_SPEC>,
pub _0_txpktu_h_dscr: Reg<_0_TXPKTU_H_DSCR_SPEC>,
pub _0_txpktu_e_dscr: Reg<_0_TXPKTU_E_DSCR_SPEC>,
pub _0_rxpktu_h_dscr: Reg<_0_RXPKTU_H_DSCR_SPEC>,
pub _0_rxpktu_e_dscr: Reg<_0_RXPKTU_E_DSCR_SPEC>,
pub seq_position: Reg<SEQ_POSITION_SPEC>,
pub _0_dscr_rec_conf: Reg<_0_DSCR_REC_CONF_SPEC>,
pub sdio_crc_st0: Reg<SDIO_CRC_ST0_SPEC>,
pub sdio_crc_st1: Reg<SDIO_CRC_ST1_SPEC>,
pub _0_eof_start_des: Reg<_0_EOF_START_DES_SPEC>,
pub _0_push_dscr_addr: Reg<_0_PUSH_DSCR_ADDR_SPEC>,
pub _0_done_dscr_addr: Reg<_0_DONE_DSCR_ADDR_SPEC>,
pub _0_sub_start_des: Reg<_0_SUB_START_DES_SPEC>,
pub _0_dscr_cnt: Reg<_0_DSCR_CNT_SPEC>,
pub _0_len_lim_conf: Reg<_0_LEN_LIM_CONF_SPEC>,
pub _0int_st1: Reg<_0INT_ST1_SPEC>,
pub _0int_ena1: Reg<_0INT_ENA1_SPEC>,
pub _1int_st1: Reg<_1INT_ST1_SPEC>,
pub _1int_ena1: Reg<_1INT_ENA1_SPEC>,
pub date: Reg<DATE_SPEC>,
pub id: Reg<ID_SPEC>,
/* private fields */
}Expand description
Register block
Fields
conf0: Reg<CONF0_SPEC>0x00 -
_0int_raw: Reg<_0INT_RAW_SPEC>0x04 -
_0int_st: Reg<_0INT_ST_SPEC>0x08 -
_0int_ena: Reg<_0INT_ENA_SPEC>0x0c -
_0int_clr: Reg<_0INT_CLR_SPEC>0x10 -
_1int_raw: Reg<_1INT_RAW_SPEC>0x14 -
_1int_st: Reg<_1INT_ST_SPEC>0x18 -
_1int_ena: Reg<_1INT_ENA_SPEC>0x1c -
_1int_clr: Reg<_1INT_CLR_SPEC>0x20 -
rx_status: Reg<RX_STATUS_SPEC>0x24 -
_0rxfifo_push: Reg<_0RXFIFO_PUSH_SPEC>0x28 -
_1rxfifo_push: Reg<_1RXFIFO_PUSH_SPEC>0x2c -
tx_status: Reg<TX_STATUS_SPEC>0x30 -
_0txfifo_pop: Reg<_0TXFIFO_POP_SPEC>0x34 -
_1txfifo_pop: Reg<_1TXFIFO_POP_SPEC>0x38 -
_0rx_link: Reg<_0RX_LINK_SPEC>0x3c -
_0tx_link: Reg<_0TX_LINK_SPEC>0x40 -
_1rx_link: Reg<_1RX_LINK_SPEC>0x44 -
_1tx_link: Reg<_1TX_LINK_SPEC>0x48 -
intvec_tohost: Reg<INTVEC_TOHOST_SPEC>0x4c -
_0token0: Reg<_0TOKEN0_SPEC>0x50 -
_0token1: Reg<_0TOKEN1_SPEC>0x54 -
_1token0: Reg<_1TOKEN0_SPEC>0x58 -
_1token1: Reg<_1TOKEN1_SPEC>0x5c -
conf1: Reg<CONF1_SPEC>0x60 -
_0_state0: Reg<_0_STATE0_SPEC>0x64 -
_0_state1: Reg<_0_STATE1_SPEC>0x68 -
_1_state0: Reg<_1_STATE0_SPEC>0x6c -
_1_state1: Reg<_1_STATE1_SPEC>0x70 -
bridge_conf: Reg<BRIDGE_CONF_SPEC>0x74 -
_0_to_eof_des_addr: Reg<_0_TO_EOF_DES_ADDR_SPEC>0x78 -
_0_tx_eof_des_addr: Reg<_0_TX_EOF_DES_ADDR_SPEC>0x7c -
_0_to_eof_bfr_des_addr: Reg<_0_TO_EOF_BFR_DES_ADDR_SPEC>0x80 -
_1_to_eof_des_addr: Reg<_1_TO_EOF_DES_ADDR_SPEC>0x84 -
_1_tx_eof_des_addr: Reg<_1_TX_EOF_DES_ADDR_SPEC>0x88 -
_1_to_eof_bfr_des_addr: Reg<_1_TO_EOF_BFR_DES_ADDR_SPEC>0x8c -
ahb_test: Reg<AHB_TEST_SPEC>0x90 -
sdio_st: Reg<SDIO_ST_SPEC>0x94 -
rx_dscr_conf: Reg<RX_DSCR_CONF_SPEC>0x98 -
_0_txlink_dscr: Reg<_0_TXLINK_DSCR_SPEC>0x9c -
_0_txlink_dscr_bf0: Reg<_0_TXLINK_DSCR_BF0_SPEC>0xa0 -
_0_txlink_dscr_bf1: Reg<_0_TXLINK_DSCR_BF1_SPEC>0xa4 -
_0_rxlink_dscr: Reg<_0_RXLINK_DSCR_SPEC>0xa8 -
_0_rxlink_dscr_bf0: Reg<_0_RXLINK_DSCR_BF0_SPEC>0xac -
_0_rxlink_dscr_bf1: Reg<_0_RXLINK_DSCR_BF1_SPEC>0xb0 -
_1_txlink_dscr: Reg<_1_TXLINK_DSCR_SPEC>0xb4 -
_1_txlink_dscr_bf0: Reg<_1_TXLINK_DSCR_BF0_SPEC>0xb8 -
_1_txlink_dscr_bf1: Reg<_1_TXLINK_DSCR_BF1_SPEC>0xbc -
_1_rxlink_dscr: Reg<_1_RXLINK_DSCR_SPEC>0xc0 -
_1_rxlink_dscr_bf0: Reg<_1_RXLINK_DSCR_BF0_SPEC>0xc4 -
_1_rxlink_dscr_bf1: Reg<_1_RXLINK_DSCR_BF1_SPEC>0xc8 -
_0_tx_erreof_des_addr: Reg<_0_TX_ERREOF_DES_ADDR_SPEC>0xcc -
_1_tx_erreof_des_addr: Reg<_1_TX_ERREOF_DES_ADDR_SPEC>0xd0 -
token_lat: Reg<TOKEN_LAT_SPEC>0xd4 -
tx_dscr_conf: Reg<TX_DSCR_CONF_SPEC>0xd8 -
cmd_infor0: Reg<CMD_INFOR0_SPEC>0xdc -
cmd_infor1: Reg<CMD_INFOR1_SPEC>0xe0 -
_0_len_conf: Reg<_0_LEN_CONF_SPEC>0xe4 -
_0_length: Reg<_0_LENGTH_SPEC>0xe8 -
_0_txpkt_h_dscr: Reg<_0_TXPKT_H_DSCR_SPEC>0xec -
_0_txpkt_e_dscr: Reg<_0_TXPKT_E_DSCR_SPEC>0xf0 -
_0_rxpkt_h_dscr: Reg<_0_RXPKT_H_DSCR_SPEC>0xf4 -
_0_rxpkt_e_dscr: Reg<_0_RXPKT_E_DSCR_SPEC>0xf8 -
_0_txpktu_h_dscr: Reg<_0_TXPKTU_H_DSCR_SPEC>0xfc -
_0_txpktu_e_dscr: Reg<_0_TXPKTU_E_DSCR_SPEC>0x100 -
_0_rxpktu_h_dscr: Reg<_0_RXPKTU_H_DSCR_SPEC>0x104 -
_0_rxpktu_e_dscr: Reg<_0_RXPKTU_E_DSCR_SPEC>0x108 -
seq_position: Reg<SEQ_POSITION_SPEC>0x114 -
_0_dscr_rec_conf: Reg<_0_DSCR_REC_CONF_SPEC>0x118 -
sdio_crc_st0: Reg<SDIO_CRC_ST0_SPEC>0x11c -
sdio_crc_st1: Reg<SDIO_CRC_ST1_SPEC>0x120 -
_0_eof_start_des: Reg<_0_EOF_START_DES_SPEC>0x124 -
_0_push_dscr_addr: Reg<_0_PUSH_DSCR_ADDR_SPEC>0x128 -
_0_done_dscr_addr: Reg<_0_DONE_DSCR_ADDR_SPEC>0x12c -
_0_sub_start_des: Reg<_0_SUB_START_DES_SPEC>0x130 -
_0_dscr_cnt: Reg<_0_DSCR_CNT_SPEC>0x134 -
_0_len_lim_conf: Reg<_0_LEN_LIM_CONF_SPEC>0x138 -
_0int_st1: Reg<_0INT_ST1_SPEC>0x13c -
_0int_ena1: Reg<_0INT_ENA1_SPEC>0x140 -
_1int_st1: Reg<_1INT_ST1_SPEC>0x144 -
_1int_ena1: Reg<_1INT_ENA1_SPEC>0x148 -
date: Reg<DATE_SPEC>0x1f8 -
id: Reg<ID_SPEC>0x1fc -
Auto Trait Implementations
impl !RefUnwindSafe for RegisterBlock
impl Send for RegisterBlock
impl !Sync for RegisterBlock
impl Unpin for RegisterBlock
impl UnwindSafe for RegisterBlock
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more