pub struct W(_);Expand description
Register CTRL writer
Implementations
sourceimpl W
impl W
sourcepub fn fcs_crc_en(&mut self) -> FCS_CRC_EN_W<'_>
pub fn fcs_crc_en(&mut self) -> FCS_CRC_EN_W<'_>
Bit 10 - For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.
sourcepub fn tx_crc_en(&mut self) -> TX_CRC_EN_W<'_>
pub fn tx_crc_en(&mut self) -> TX_CRC_EN_W<'_>
Bit 11 - For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable
sourcepub fn wait_flash_idle_en(&mut self) -> WAIT_FLASH_IDLE_EN_W<'_>
pub fn wait_flash_idle_en(&mut self) -> WAIT_FLASH_IDLE_EN_W<'_>
Bit 12 - wait flash idle when program flash or erase flash. 1: enable 0: disable.
sourcepub fn fastrd_mode(&mut self) -> FASTRD_MODE_W<'_>
pub fn fastrd_mode(&mut self) -> FASTRD_MODE_W<'_>
Bit 13 - This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable.
sourcepub fn fread_dual(&mut self) -> FREAD_DUAL_W<'_>
pub fn fread_dual(&mut self) -> FREAD_DUAL_W<'_>
Bit 14 - In the read operations read-data phase apply 2 signals. 1: enable 0: disable.
sourcepub fn resandres(&mut self) -> RESANDRES_W<'_>
pub fn resandres(&mut self) -> RESANDRES_W<'_>
Bit 15 - The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable.
sourcepub fn fread_quad(&mut self) -> FREAD_QUAD_W<'_>
pub fn fread_quad(&mut self) -> FREAD_QUAD_W<'_>
Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
sourcepub fn wp(&mut self) -> WP_W<'_>
pub fn wp(&mut self) -> WP_W<'_>
Bit 21 - Write protect signal output when SPI is idle. 1: output high 0: output low.
sourcepub fn wrsr_2b(&mut self) -> WRSR_2B_W<'_>
pub fn wrsr_2b(&mut self) -> WRSR_2B_W<'_>
Bit 22 - two bytes data will be written to status register when it is set. 1: enable 0: disable.
sourcepub fn fread_dio(&mut self) -> FREAD_DIO_W<'_>
pub fn fread_dio(&mut self) -> FREAD_DIO_W<'_>
Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.
sourcepub fn fread_qio(&mut self) -> FREAD_QIO_W<'_>
pub fn fread_qio(&mut self) -> FREAD_QIO_W<'_>
Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.
sourcepub fn rd_bit_order(&mut self) -> RD_BIT_ORDER_W<'_>
pub fn rd_bit_order(&mut self) -> RD_BIT_ORDER_W<'_>
Bit 25 - In read-data (MISO) phase 1: LSB first 0: MSB first
sourcepub fn wr_bit_order(&mut self) -> WR_BIT_ORDER_W<'_>
pub fn wr_bit_order(&mut self) -> WR_BIT_ORDER_W<'_>
Bit 26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first
Methods from Deref<Target = W<CTRL_SPEC>>
Trait Implementations
Auto Trait Implementations
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more