pub struct W(_);Expand description
Register CACHE_IA_INT_EN writer
Implementations
sourceimpl W
impl W
sourcepub fn cache_ia_int_en(&mut self) -> CACHE_IA_INT_EN_W<'_>
pub fn cache_ia_int_en(&mut self) -> CACHE_IA_INT_EN_W<'_>
Bits 0:27 - Interrupt enable bits for various invalid cache access reasons
sourcepub fn cache_ia_int_app_drom0(&mut self) -> CACHE_IA_INT_APP_DROM0_W<'_>
pub fn cache_ia_int_app_drom0(&mut self) -> CACHE_IA_INT_APP_DROM0_W<'_>
Bit 0 - APP CPU invalid access to DROM0 when cache is disabled
sourcepub fn cache_ia_int_app_iram0(&mut self) -> CACHE_IA_INT_APP_IRAM0_W<'_>
pub fn cache_ia_int_app_iram0(&mut self) -> CACHE_IA_INT_APP_IRAM0_W<'_>
Bit 1 - APP CPU invalid access to IRAM0 when cache is disabled
sourcepub fn cache_ia_int_app_iram1(&mut self) -> CACHE_IA_INT_APP_IRAM1_W<'_>
pub fn cache_ia_int_app_iram1(&mut self) -> CACHE_IA_INT_APP_IRAM1_W<'_>
Bit 2 - APP CPU invalid access to IRAM1 when cache is disabled
sourcepub fn cache_ia_int_app_irom0(&mut self) -> CACHE_IA_INT_APP_IROM0_W<'_>
pub fn cache_ia_int_app_irom0(&mut self) -> CACHE_IA_INT_APP_IROM0_W<'_>
Bit 3 - APP CPU invalid access to IROM0 when cache is disabled
sourcepub fn cache_ia_int_app_dram1(&mut self) -> CACHE_IA_INT_APP_DRAM1_W<'_>
pub fn cache_ia_int_app_dram1(&mut self) -> CACHE_IA_INT_APP_DRAM1_W<'_>
Bit 4 - APP CPU invalid access to DRAM1 when cache is disabled
sourcepub fn cache_ia_int_app_opposite(&mut self) -> CACHE_IA_INT_APP_OPPOSITE_W<'_>
pub fn cache_ia_int_app_opposite(&mut self) -> CACHE_IA_INT_APP_OPPOSITE_W<'_>
Bit 5 - APP CPU invalid access to APP CPU cache when cache disabled
sourcepub fn cache_ia_int_pro_drom0(&mut self) -> CACHE_IA_INT_PRO_DROM0_W<'_>
pub fn cache_ia_int_pro_drom0(&mut self) -> CACHE_IA_INT_PRO_DROM0_W<'_>
Bit 14 - PRO CPU invalid access to DROM0 when cache is disabled
sourcepub fn cache_ia_int_pro_iram0(&mut self) -> CACHE_IA_INT_PRO_IRAM0_W<'_>
pub fn cache_ia_int_pro_iram0(&mut self) -> CACHE_IA_INT_PRO_IRAM0_W<'_>
Bit 15 - PRO CPU invalid access to IRAM0 when cache is disabled
sourcepub fn cache_ia_int_pro_iram1(&mut self) -> CACHE_IA_INT_PRO_IRAM1_W<'_>
pub fn cache_ia_int_pro_iram1(&mut self) -> CACHE_IA_INT_PRO_IRAM1_W<'_>
Bit 16 - PRO CPU invalid access to IRAM1 when cache is disabled
sourcepub fn cache_ia_int_pro_irom0(&mut self) -> CACHE_IA_INT_PRO_IROM0_W<'_>
pub fn cache_ia_int_pro_irom0(&mut self) -> CACHE_IA_INT_PRO_IROM0_W<'_>
Bit 17 - PRO CPU invalid access to IROM0 when cache is disabled
sourcepub fn cache_ia_int_pro_dram1(&mut self) -> CACHE_IA_INT_PRO_DRAM1_W<'_>
pub fn cache_ia_int_pro_dram1(&mut self) -> CACHE_IA_INT_PRO_DRAM1_W<'_>
Bit 18 - PRO CPU invalid access to DRAM1 when cache is disabled
sourcepub fn cache_ia_int_pro_opposite(&mut self) -> CACHE_IA_INT_PRO_OPPOSITE_W<'_>
pub fn cache_ia_int_pro_opposite(&mut self) -> CACHE_IA_INT_PRO_OPPOSITE_W<'_>
Bit 19 - PRO CPU invalid access to APP CPU cache when cache disabled
Methods from Deref<Target = W<CACHE_IA_INT_EN_SPEC>>
Trait Implementations
sourceimpl From<W<CACHE_IA_INT_EN_SPEC>> for W
impl From<W<CACHE_IA_INT_EN_SPEC>> for W
sourcefn from(writer: W<CACHE_IA_INT_EN_SPEC>) -> Self
fn from(writer: W<CACHE_IA_INT_EN_SPEC>) -> Self
Converts to this type from the input type.
Auto Trait Implementations
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more