Files
esp32
aes
apb_ctrl
dport
access_check.rsahb_lite_mask.rsahb_mpu_table_0.rsahb_mpu_table_1.rsahblite_mpu_table_apb_ctrl.rsahblite_mpu_table_bb.rsahblite_mpu_table_bt.rsahblite_mpu_table_bt_buffer.rsahblite_mpu_table_btmac.rsahblite_mpu_table_can.rsahblite_mpu_table_efuse.rsahblite_mpu_table_emac.rsahblite_mpu_table_fe.rsahblite_mpu_table_fe2.rsahblite_mpu_table_gpio.rsahblite_mpu_table_hinf.rsahblite_mpu_table_i2c.rsahblite_mpu_table_i2c_ext0.rsahblite_mpu_table_i2c_ext1.rsahblite_mpu_table_i2s0.rsahblite_mpu_table_i2s1.rsahblite_mpu_table_io_mux.rsahblite_mpu_table_ledc.rsahblite_mpu_table_misc.rsahblite_mpu_table_pcnt.rsahblite_mpu_table_pwm0.rsahblite_mpu_table_pwm1.rsahblite_mpu_table_pwm2.rsahblite_mpu_table_pwm3.rsahblite_mpu_table_pwr.rsahblite_mpu_table_rmt.rsahblite_mpu_table_rtc.rsahblite_mpu_table_rwbt.rsahblite_mpu_table_sdio_host.rsahblite_mpu_table_slc.rsahblite_mpu_table_slchost.rsahblite_mpu_table_spi0.rsahblite_mpu_table_spi1.rsahblite_mpu_table_spi2.rsahblite_mpu_table_spi3.rsahblite_mpu_table_spi_encrypt.rsahblite_mpu_table_timer.rsahblite_mpu_table_timergroup.rsahblite_mpu_table_timergroup1.rsahblite_mpu_table_uart.rsahblite_mpu_table_uart1.rsahblite_mpu_table_uart2.rsahblite_mpu_table_uhci0.rsahblite_mpu_table_uhci1.rsahblite_mpu_table_wdg.rsahblite_mpu_table_wifimac.rsapp_bb_int_map.rsapp_boot_remap_ctrl.rsapp_bt_bb_int_map.rsapp_bt_bb_nmi_map.rsapp_bt_mac_int_map.rsapp_cache_ctrl.rsapp_cache_ctrl1.rsapp_cache_ia_int_map.rsapp_cache_lock_0_addr.rsapp_cache_lock_1_addr.rsapp_cache_lock_2_addr.rsapp_cache_lock_3_addr.rsapp_can_int_map.rsapp_cpu_intr_from_cpu_0_map.rsapp_cpu_intr_from_cpu_1_map.rsapp_cpu_intr_from_cpu_2_map.rsapp_cpu_intr_from_cpu_3_map.rsapp_cpu_record_ctrl.rsapp_cpu_record_pdebugdata.rsapp_cpu_record_pdebuginst.rsapp_cpu_record_pdebugls0addr.rsapp_cpu_record_pdebugls0data.rsapp_cpu_record_pdebugls0stat.rsapp_cpu_record_pdebugpc.rsapp_cpu_record_pdebugstatus.rsapp_cpu_record_pid.rsapp_cpu_record_status.rsapp_dcache_dbug0.rsapp_dcache_dbug1.rsapp_dcache_dbug2.rsapp_dcache_dbug3.rsapp_dcache_dbug4.rsapp_dcache_dbug5.rsapp_dcache_dbug6.rsapp_dcache_dbug7.rsapp_dcache_dbug8.rsapp_dcache_dbug9.rsapp_dport_apb_mask0.rsapp_dport_apb_mask1.rsapp_efuse_int_map.rsapp_emac_int_map.rsapp_gpio_interrupt_map.rsapp_gpio_interrupt_nmi_map.rsapp_i2c_ext0_intr_map.rsapp_i2c_ext1_intr_map.rsapp_i2s0_int_map.rsapp_i2s1_int_map.rsapp_intr_status_0.rsapp_intr_status_1.rsapp_intr_status_2.rsapp_intrusion_ctrl.rsapp_intrusion_status.rsapp_ledc_int_map.rsapp_mac_intr_map.rsapp_mac_nmi_map.rsapp_mmu_ia_int_map.rsapp_mpu_ia_int_map.rsapp_pcnt_intr_map.rsapp_pwm0_intr_map.rsapp_pwm1_intr_map.rsapp_pwm2_intr_map.rsapp_pwm3_intr_map.rsapp_rmt_intr_map.rsapp_rsa_intr_map.rsapp_rtc_core_intr_map.rsapp_rwble_irq_map.rsapp_rwble_nmi_map.rsapp_rwbt_irq_map.rsapp_rwbt_nmi_map.rsapp_sdio_host_interrupt_map.rsapp_slc0_intr_map.rsapp_slc1_intr_map.rsapp_spi1_dma_int_map.rsapp_spi2_dma_int_map.rsapp_spi3_dma_int_map.rsapp_spi_intr_0_map.rsapp_spi_intr_1_map.rsapp_spi_intr_2_map.rsapp_spi_intr_3_map.rsapp_tg1_lact_edge_int_map.rsapp_tg1_lact_level_int_map.rsapp_tg1_t0_edge_int_map.rsapp_tg1_t0_level_int_map.rsapp_tg1_t1_edge_int_map.rsapp_tg1_t1_level_int_map.rsapp_tg1_wdt_edge_int_map.rsapp_tg1_wdt_level_int_map.rsapp_tg_lact_edge_int_map.rsapp_tg_lact_level_int_map.rsapp_tg_t0_edge_int_map.rsapp_tg_t0_level_int_map.rsapp_tg_t1_edge_int_map.rsapp_tg_t1_level_int_map.rsapp_tg_wdt_edge_int_map.rsapp_tg_wdt_level_int_map.rsapp_timer_int1_map.rsapp_timer_int2_map.rsapp_tracemem_ena.rsapp_uart1_intr_map.rsapp_uart2_intr_map.rsapp_uart_intr_map.rsapp_uhci0_intr_map.rsapp_uhci1_intr_map.rsapp_vecbase_ctrl.rsapp_vecbase_set.rsapp_wdg_int_map.rsappcpu_ctrl_a.rsappcpu_ctrl_b.rsappcpu_ctrl_c.rsappcpu_ctrl_d.rsbt_lpck_div_frac.rsbt_lpck_div_int.rscache_ia_int_en.rscache_mux_mode.rscore_rst_en.rscpu_intr_from_cpu_0.rscpu_intr_from_cpu_1.rscpu_intr_from_cpu_2.rscpu_intr_from_cpu_3.rscpu_per_conf.rsdate.rsdmmu_page_mode.rsdmmu_table0.rsdmmu_table1.rsdmmu_table10.rsdmmu_table11.rsdmmu_table12.rsdmmu_table13.rsdmmu_table14.rsdmmu_table15.rsdmmu_table2.rsdmmu_table3.rsdmmu_table4.rsdmmu_table5.rsdmmu_table6.rsdmmu_table7.rsdmmu_table8.rsdmmu_table9.rsfront_end_mem_pd.rshost_inf_sel.rsimmu_page_mode.rsimmu_table0.rsimmu_table1.rsimmu_table10.rsimmu_table11.rsimmu_table12.rsimmu_table13.rsimmu_table14.rsimmu_table15.rsimmu_table2.rsimmu_table3.rsimmu_table4.rsimmu_table5.rsimmu_table6.rsimmu_table7.rsimmu_table8.rsimmu_table9.rsiram_dram_ahb_sel.rsmem_access_dbug0.rsmem_access_dbug1.rsmem_pd_mask.rsmmu_ia_int_en.rsmpu_ia_int_en.rsperi_clk_en.rsperi_rst_en.rsperip_clk_en.rsperip_rst_en.rspro_bb_int_map.rspro_boot_remap_ctrl.rspro_bt_bb_int_map.rspro_bt_bb_nmi_map.rspro_bt_mac_int_map.rspro_cache_ctrl.rspro_cache_ctrl1.rspro_cache_ia_int_map.rspro_cache_lock_0_addr.rspro_cache_lock_1_addr.rspro_cache_lock_2_addr.rspro_cache_lock_3_addr.rspro_can_int_map.rspro_cpu_intr_from_cpu_0_map.rspro_cpu_intr_from_cpu_1_map.rspro_cpu_intr_from_cpu_2_map.rspro_cpu_intr_from_cpu_3_map.rspro_cpu_record_ctrl.rspro_cpu_record_pdebugdata.rspro_cpu_record_pdebuginst.rspro_cpu_record_pdebugls0addr.rspro_cpu_record_pdebugls0data.rspro_cpu_record_pdebugls0stat.rspro_cpu_record_pdebugpc.rspro_cpu_record_pdebugstatus.rspro_cpu_record_pid.rspro_cpu_record_status.rspro_dcache_dbug0.rspro_dcache_dbug1.rspro_dcache_dbug2.rspro_dcache_dbug3.rspro_dcache_dbug4.rspro_dcache_dbug5.rspro_dcache_dbug6.rspro_dcache_dbug7.rspro_dcache_dbug8.rspro_dcache_dbug9.rspro_dport_apb_mask0.rspro_dport_apb_mask1.rspro_efuse_int_map.rspro_emac_int_map.rspro_gpio_interrupt_map.rspro_gpio_interrupt_nmi_map.rspro_i2c_ext0_intr_map.rspro_i2c_ext1_intr_map.rspro_i2s0_int_map.rspro_i2s1_int_map.rspro_intr_status_0.rspro_intr_status_1.rspro_intr_status_2.rspro_intrusion_ctrl.rspro_intrusion_status.rspro_ledc_int_map.rspro_mac_intr_map.rspro_mac_nmi_map.rspro_mmu_ia_int_map.rspro_mpu_ia_int_map.rspro_pcnt_intr_map.rspro_pwm0_intr_map.rspro_pwm1_intr_map.rspro_pwm2_intr_map.rspro_pwm3_intr_map.rspro_rmt_intr_map.rspro_rsa_intr_map.rspro_rtc_core_intr_map.rspro_rwble_irq_map.rspro_rwble_nmi_map.rspro_rwbt_irq_map.rspro_rwbt_nmi_map.rspro_sdio_host_interrupt_map.rspro_slc0_intr_map.rspro_slc1_intr_map.rspro_spi1_dma_int_map.rspro_spi2_dma_int_map.rspro_spi3_dma_int_map.rspro_spi_intr_0_map.rspro_spi_intr_1_map.rspro_spi_intr_2_map.rspro_spi_intr_3_map.rspro_tg1_lact_edge_int_map.rspro_tg1_lact_level_int_map.rspro_tg1_t0_edge_int_map.rspro_tg1_t0_level_int_map.rspro_tg1_t1_edge_int_map.rspro_tg1_t1_level_int_map.rspro_tg1_wdt_edge_int_map.rspro_tg1_wdt_level_int_map.rspro_tg_lact_edge_int_map.rspro_tg_lact_level_int_map.rspro_tg_t0_edge_int_map.rspro_tg_t0_level_int_map.rspro_tg_t1_edge_int_map.rspro_tg_t1_level_int_map.rspro_tg_wdt_edge_int_map.rspro_tg_wdt_level_int_map.rspro_timer_int1_map.rspro_timer_int2_map.rspro_tracemem_ena.rspro_uart1_intr_map.rspro_uart2_intr_map.rspro_uart_intr_map.rspro_uhci0_intr_map.rspro_uhci1_intr_map.rspro_vecbase_ctrl.rspro_vecbase_set.rspro_wdg_int_map.rsrom_fo_ctrl.rsrom_mpu_ena.rsrom_mpu_table0.rsrom_mpu_table1.rsrom_mpu_table2.rsrom_mpu_table3.rsrom_pd_ctrl.rsrsa_pd_ctrl.rssecure_boot_ctrl.rsshrom_mpu_table0.rsshrom_mpu_table1.rsshrom_mpu_table10.rsshrom_mpu_table11.rsshrom_mpu_table12.rsshrom_mpu_table13.rsshrom_mpu_table14.rsshrom_mpu_table15.rsshrom_mpu_table16.rsshrom_mpu_table17.rsshrom_mpu_table18.rsshrom_mpu_table19.rsshrom_mpu_table2.rsshrom_mpu_table20.rsshrom_mpu_table21.rsshrom_mpu_table22.rsshrom_mpu_table23.rsshrom_mpu_table3.rsshrom_mpu_table4.rsshrom_mpu_table5.rsshrom_mpu_table6.rsshrom_mpu_table7.rsshrom_mpu_table8.rsshrom_mpu_table9.rsspi_dma_chan_sel.rssram_fo_ctrl_0.rssram_fo_ctrl_1.rssram_pd_ctrl_0.rssram_pd_ctrl_1.rstag_fo_ctrl.rstracemem_mux_mode.rswifi_bb_cfg.rswifi_bb_cfg_2.rswifi_clk_en.rs
efuse
gpio
gpio_sd
hinf
i2c
i2s
io_mux
ledc
mcpwm
pcnt
rmt
rng
rtc_i2c
rtccntl
rtcio
sens
slc
slchost
host_slc0_host_pf.rshost_slc0host_func1_int_ena.rshost_slc0host_func2_int_ena.rshost_slc0host_int_clr.rshost_slc0host_int_ena.rshost_slc0host_int_ena1.rshost_slc0host_int_raw.rshost_slc0host_int_st.rshost_slc0host_len_wd.rshost_slc0host_rx_infor.rshost_slc0host_token_rdata.rshost_slc0host_token_wdata.rshost_slc1_host_pf.rshost_slc1host_func1_int_ena.rshost_slc1host_func2_int_ena.rshost_slc1host_int_clr.rshost_slc1host_int_ena.rshost_slc1host_int_ena1.rshost_slc1host_int_raw.rshost_slc1host_int_st.rshost_slc1host_rx_infor.rshost_slc1host_token_rdata.rshost_slc1host_token_wdata.rshost_slc_apbwin_conf.rshost_slc_apbwin_rdata.rshost_slc_apbwin_wdata.rshost_slchost_check_sum0.rshost_slchost_check_sum1.rshost_slchost_conf.rshost_slchost_conf_w0.rshost_slchost_conf_w1.rshost_slchost_conf_w10.rshost_slchost_conf_w11.rshost_slchost_conf_w12.rshost_slchost_conf_w13.rshost_slchost_conf_w14.rshost_slchost_conf_w15.rshost_slchost_conf_w2.rshost_slchost_conf_w3.rshost_slchost_conf_w4.rshost_slchost_conf_w5.rshost_slchost_conf_w6.rshost_slchost_conf_w7.rshost_slchost_conf_w8.rshost_slchost_conf_w9.rshost_slchost_func2_0.rshost_slchost_func2_1.rshost_slchost_func2_2.rshost_slchost_gpio_in0.rshost_slchost_gpio_in1.rshost_slchost_gpio_status0.rshost_slchost_gpio_status1.rshost_slchost_inf_st.rshost_slchost_pkt_len.rshost_slchost_pkt_len0.rshost_slchost_pkt_len1.rshost_slchost_pkt_len2.rshost_slchost_rdclr0.rshost_slchost_rdclr1.rshost_slchost_state_w0.rshost_slchost_state_w1.rshost_slchost_token_con.rshost_slchostdate.rshost_slchostid.rs
spi
syscon
timg
uart
uhci
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#[doc = "Register `PIN_CTRL` reader"]
pub struct R(crate::R<PIN_CTRL_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<PIN_CTRL_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<PIN_CTRL_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<PIN_CTRL_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `PIN_CTRL` writer"]
pub struct W(crate::W<PIN_CTRL_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<PIN_CTRL_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl From<crate::W<PIN_CTRL_SPEC>> for W {
    #[inline(always)]
    fn from(writer: crate::W<PIN_CTRL_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `PIN_CTRL_CLK3` reader - "]
pub struct PIN_CTRL_CLK3_R(crate::FieldReader<u8, u8>);
impl PIN_CTRL_CLK3_R {
    pub(crate) fn new(bits: u8) -> Self {
        PIN_CTRL_CLK3_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for PIN_CTRL_CLK3_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `PIN_CTRL_CLK3` writer - "]
pub struct PIN_CTRL_CLK3_W<'a> {
    w: &'a mut W,
}
impl<'a> PIN_CTRL_CLK3_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8);
        self.w
    }
}
#[doc = "Field `PIN_CTRL_CLK2` reader - "]
pub struct PIN_CTRL_CLK2_R(crate::FieldReader<u8, u8>);
impl PIN_CTRL_CLK2_R {
    pub(crate) fn new(bits: u8) -> Self {
        PIN_CTRL_CLK2_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for PIN_CTRL_CLK2_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `PIN_CTRL_CLK2` writer - "]
pub struct PIN_CTRL_CLK2_W<'a> {
    w: &'a mut W,
}
impl<'a> PIN_CTRL_CLK2_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4);
        self.w
    }
}
#[doc = "Field `PIN_CTRL_CLK1` reader - "]
pub struct PIN_CTRL_CLK1_R(crate::FieldReader<u8, u8>);
impl PIN_CTRL_CLK1_R {
    pub(crate) fn new(bits: u8) -> Self {
        PIN_CTRL_CLK1_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for PIN_CTRL_CLK1_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `PIN_CTRL_CLK1` writer - "]
pub struct PIN_CTRL_CLK1_W<'a> {
    w: &'a mut W,
}
impl<'a> PIN_CTRL_CLK1_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07);
        self.w
    }
}
impl R {
    #[doc = "Bits 8:10"]
    #[inline(always)]
    pub fn pin_ctrl_clk3(&self) -> PIN_CTRL_CLK3_R {
        PIN_CTRL_CLK3_R::new(((self.bits >> 8) & 0x07) as u8)
    }
    #[doc = "Bits 4:6"]
    #[inline(always)]
    pub fn pin_ctrl_clk2(&self) -> PIN_CTRL_CLK2_R {
        PIN_CTRL_CLK2_R::new(((self.bits >> 4) & 0x07) as u8)
    }
    #[doc = "Bits 0:2"]
    #[inline(always)]
    pub fn pin_ctrl_clk1(&self) -> PIN_CTRL_CLK1_R {
        PIN_CTRL_CLK1_R::new((self.bits & 0x07) as u8)
    }
}
impl W {
    #[doc = "Bits 8:10"]
    #[inline(always)]
    pub fn pin_ctrl_clk3(&mut self) -> PIN_CTRL_CLK3_W {
        PIN_CTRL_CLK3_W { w: self }
    }
    #[doc = "Bits 4:6"]
    #[inline(always)]
    pub fn pin_ctrl_clk2(&mut self) -> PIN_CTRL_CLK2_W {
        PIN_CTRL_CLK2_W { w: self }
    }
    #[doc = "Bits 0:2"]
    #[inline(always)]
    pub fn pin_ctrl_clk1(&mut self) -> PIN_CTRL_CLK1_W {
        PIN_CTRL_CLK1_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "configures clock source and clock output pins\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pin_ctrl](index.html) module"]
pub struct PIN_CTRL_SPEC;
impl crate::RegisterSpec for PIN_CTRL_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [pin_ctrl::R](R) reader structure"]
impl crate::Readable for PIN_CTRL_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [pin_ctrl::W](W) writer structure"]
impl crate::Writable for PIN_CTRL_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets PIN_CTRL to value 0"]
impl crate::Resettable for PIN_CTRL_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}