[][src]Struct esp32::uhci::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub conf0: Reg<CONF0_SPEC>,
    pub int_raw: Reg<INT_RAW_SPEC>,
    pub int_st: Reg<INT_ST_SPEC>,
    pub int_ena: Reg<INT_ENA_SPEC>,
    pub int_clr: Reg<INT_CLR_SPEC>,
    pub dma_out_status: Reg<DMA_OUT_STATUS_SPEC>,
    pub dma_out_push: Reg<DMA_OUT_PUSH_SPEC>,
    pub dma_in_status: Reg<DMA_IN_STATUS_SPEC>,
    pub dma_in_pop: Reg<DMA_IN_POP_SPEC>,
    pub dma_out_link: Reg<DMA_OUT_LINK_SPEC>,
    pub dma_in_link: Reg<DMA_IN_LINK_SPEC>,
    pub conf1: Reg<CONF1_SPEC>,
    pub state0: Reg<STATE0_SPEC>,
    pub state1: Reg<STATE1_SPEC>,
    pub dma_out_eof_des_addr: Reg<DMA_OUT_EOF_DES_ADDR_SPEC>,
    pub dma_in_suc_eof_des_addr: Reg<DMA_IN_SUC_EOF_DES_ADDR_SPEC>,
    pub dma_in_err_eof_des_addr: Reg<DMA_IN_ERR_EOF_DES_ADDR_SPEC>,
    pub dma_out_eof_bfr_des_addr: Reg<DMA_OUT_EOF_BFR_DES_ADDR_SPEC>,
    pub ahb_test: Reg<AHB_TEST_SPEC>,
    pub dma_in_dscr: Reg<DMA_IN_DSCR_SPEC>,
    pub dma_in_dscr_bf0: Reg<DMA_IN_DSCR_BF0_SPEC>,
    pub dma_in_dscr_bf1: Reg<DMA_IN_DSCR_BF1_SPEC>,
    pub dma_out_dscr: Reg<DMA_OUT_DSCR_SPEC>,
    pub dma_out_dscr_bf0: Reg<DMA_OUT_DSCR_BF0_SPEC>,
    pub dma_out_dscr_bf1: Reg<DMA_OUT_DSCR_BF1_SPEC>,
    pub escape_conf: Reg<ESCAPE_CONF_SPEC>,
    pub hung_conf: Reg<HUNG_CONF_SPEC>,
    pub rx_head: Reg<RX_HEAD_SPEC>,
    pub quick_sent: Reg<QUICK_SENT_SPEC>,
    pub q0_word0: Reg<Q0_WORD0_SPEC>,
    pub q0_word1: Reg<Q0_WORD1_SPEC>,
    pub q1_word0: Reg<Q1_WORD0_SPEC>,
    pub q1_word1: Reg<Q1_WORD1_SPEC>,
    pub q2_word0: Reg<Q2_WORD0_SPEC>,
    pub q2_word1: Reg<Q2_WORD1_SPEC>,
    pub q3_word0: Reg<Q3_WORD0_SPEC>,
    pub q3_word1: Reg<Q3_WORD1_SPEC>,
    pub q4_word0: Reg<Q4_WORD0_SPEC>,
    pub q4_word1: Reg<Q4_WORD1_SPEC>,
    pub q5_word0: Reg<Q5_WORD0_SPEC>,
    pub q5_word1: Reg<Q5_WORD1_SPEC>,
    pub q6_word0: Reg<Q6_WORD0_SPEC>,
    pub q6_word1: Reg<Q6_WORD1_SPEC>,
    pub esc_conf0: Reg<ESC_CONF0_SPEC>,
    pub esc_conf1: Reg<ESC_CONF1_SPEC>,
    pub esc_conf2: Reg<ESC_CONF2_SPEC>,
    pub esc_conf3: Reg<ESC_CONF3_SPEC>,
    pub pkt_thres: Reg<PKT_THRES_SPEC>,
    pub date: Reg<DATE_SPEC>,
    // some fields omitted
}

Register block

Fields

conf0: Reg<CONF0_SPEC>

0x00 - UHCI_CONF0

int_raw: Reg<INT_RAW_SPEC>

0x04 - UHCI_INT_RAW

int_st: Reg<INT_ST_SPEC>

0x08 - UHCI_INT_ST

int_ena: Reg<INT_ENA_SPEC>

0x0c - UHCI_INT_ENA

int_clr: Reg<INT_CLR_SPEC>

0x10 - UHCI_INT_CLR

dma_out_status: Reg<DMA_OUT_STATUS_SPEC>

0x14 - UHCI_DMA_OUT_STATUS

dma_out_push: Reg<DMA_OUT_PUSH_SPEC>

0x18 - UHCI_DMA_OUT_PUSH

dma_in_status: Reg<DMA_IN_STATUS_SPEC>

0x1c - UHCI_DMA_IN_STATUS

dma_in_pop: Reg<DMA_IN_POP_SPEC>

0x20 - UHCI_DMA_IN_POP

dma_out_link: Reg<DMA_OUT_LINK_SPEC>

0x24 - UHCI_DMA_OUT_LINK

dma_in_link: Reg<DMA_IN_LINK_SPEC>

0x28 - UHCI_DMA_IN_LINK

conf1: Reg<CONF1_SPEC>

0x2c - UHCI_CONF1

state0: Reg<STATE0_SPEC>

0x30 - UHCI_STATE0

state1: Reg<STATE1_SPEC>

0x34 - UHCI_STATE1

dma_out_eof_des_addr: Reg<DMA_OUT_EOF_DES_ADDR_SPEC>

0x38 - UHCI_DMA_OUT_EOF_DES_ADDR

dma_in_suc_eof_des_addr: Reg<DMA_IN_SUC_EOF_DES_ADDR_SPEC>

0x3c - UHCI_DMA_IN_SUC_EOF_DES_ADDR

dma_in_err_eof_des_addr: Reg<DMA_IN_ERR_EOF_DES_ADDR_SPEC>

0x40 - UHCI_DMA_IN_ERR_EOF_DES_ADDR

dma_out_eof_bfr_des_addr: Reg<DMA_OUT_EOF_BFR_DES_ADDR_SPEC>

0x44 - UHCI_DMA_OUT_EOF_BFR_DES_ADDR

ahb_test: Reg<AHB_TEST_SPEC>

0x48 - UHCI_AHB_TEST

dma_in_dscr: Reg<DMA_IN_DSCR_SPEC>

0x4c - UHCI_DMA_IN_DSCR

dma_in_dscr_bf0: Reg<DMA_IN_DSCR_BF0_SPEC>

0x50 - UHCI_DMA_IN_DSCR_BF0

dma_in_dscr_bf1: Reg<DMA_IN_DSCR_BF1_SPEC>

0x54 - UHCI_DMA_IN_DSCR_BF1

dma_out_dscr: Reg<DMA_OUT_DSCR_SPEC>

0x58 - UHCI_DMA_OUT_DSCR

dma_out_dscr_bf0: Reg<DMA_OUT_DSCR_BF0_SPEC>

0x5c - UHCI_DMA_OUT_DSCR_BF0

dma_out_dscr_bf1: Reg<DMA_OUT_DSCR_BF1_SPEC>

0x60 - UHCI_DMA_OUT_DSCR_BF1

escape_conf: Reg<ESCAPE_CONF_SPEC>

0x64 - UHCI_ESCAPE_CONF

hung_conf: Reg<HUNG_CONF_SPEC>

0x68 - UHCI_HUNG_CONF

rx_head: Reg<RX_HEAD_SPEC>

0x70 - UHCI_RX_HEAD

quick_sent: Reg<QUICK_SENT_SPEC>

0x74 - UHCI_QUICK_SENT

q0_word0: Reg<Q0_WORD0_SPEC>

0x78 - UHCI_Q0_WORD0

q0_word1: Reg<Q0_WORD1_SPEC>

0x7c - UHCI_Q0_WORD1

q1_word0: Reg<Q1_WORD0_SPEC>

0x80 - UHCI_Q1_WORD0

q1_word1: Reg<Q1_WORD1_SPEC>

0x84 - UHCI_Q1_WORD1

q2_word0: Reg<Q2_WORD0_SPEC>

0x88 - UHCI_Q2_WORD0

q2_word1: Reg<Q2_WORD1_SPEC>

0x8c - UHCI_Q2_WORD1

q3_word0: Reg<Q3_WORD0_SPEC>

0x90 - UHCI_Q3_WORD0

q3_word1: Reg<Q3_WORD1_SPEC>

0x94 - UHCI_Q3_WORD1

q4_word0: Reg<Q4_WORD0_SPEC>

0x98 - UHCI_Q4_WORD0

q4_word1: Reg<Q4_WORD1_SPEC>

0x9c - UHCI_Q4_WORD1

q5_word0: Reg<Q5_WORD0_SPEC>

0xa0 - UHCI_Q5_WORD0

q5_word1: Reg<Q5_WORD1_SPEC>

0xa4 - UHCI_Q5_WORD1

q6_word0: Reg<Q6_WORD0_SPEC>

0xa8 - UHCI_Q6_WORD0

q6_word1: Reg<Q6_WORD1_SPEC>

0xac - UHCI_Q6_WORD1

esc_conf0: Reg<ESC_CONF0_SPEC>

0xb0 - UHCI_ESC_CONF0

esc_conf1: Reg<ESC_CONF1_SPEC>

0xb4 - UHCI_ESC_CONF1

esc_conf2: Reg<ESC_CONF2_SPEC>

0xb8 - UHCI_ESC_CONF2

esc_conf3: Reg<ESC_CONF3_SPEC>

0xbc - UHCI_ESC_CONF3

pkt_thres: Reg<PKT_THRES_SPEC>

0xc0 - UHCI_PKT_THRES

date: Reg<DATE_SPEC>

0xfc - UHCI_DATE

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