[][src]Struct esp32::sens::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub sar_read_ctrl: Reg<SAR_READ_CTRL_SPEC>,
    pub sar_read_status1: Reg<SAR_READ_STATUS1_SPEC>,
    pub sar_meas_wait1: Reg<SAR_MEAS_WAIT1_SPEC>,
    pub sar_meas_wait2: Reg<SAR_MEAS_WAIT2_SPEC>,
    pub sar_meas_ctrl: Reg<SAR_MEAS_CTRL_SPEC>,
    pub sar_read_status2: Reg<SAR_READ_STATUS2_SPEC>,
    pub ulp_cp_sleep_cyc0: Reg<ULP_CP_SLEEP_CYC0_SPEC>,
    pub ulp_cp_sleep_cyc1: Reg<ULP_CP_SLEEP_CYC1_SPEC>,
    pub ulp_cp_sleep_cyc2: Reg<ULP_CP_SLEEP_CYC2_SPEC>,
    pub ulp_cp_sleep_cyc3: Reg<ULP_CP_SLEEP_CYC3_SPEC>,
    pub ulp_cp_sleep_cyc4: Reg<ULP_CP_SLEEP_CYC4_SPEC>,
    pub sar_start_force: Reg<SAR_START_FORCE_SPEC>,
    pub sar_mem_wr_ctrl: Reg<SAR_MEM_WR_CTRL_SPEC>,
    pub sar_atten1: Reg<SAR_ATTEN1_SPEC>,
    pub sar_atten2: Reg<SAR_ATTEN2_SPEC>,
    pub sar_slave_addr1: Reg<SAR_SLAVE_ADDR1_SPEC>,
    pub sar_slave_addr2: Reg<SAR_SLAVE_ADDR2_SPEC>,
    pub sar_slave_addr3: Reg<SAR_SLAVE_ADDR3_SPEC>,
    pub sar_slave_addr4: Reg<SAR_SLAVE_ADDR4_SPEC>,
    pub sar_tsens_ctrl: Reg<SAR_TSENS_CTRL_SPEC>,
    pub sar_i2c_ctrl: Reg<SAR_I2C_CTRL_SPEC>,
    pub sar_meas_start1: Reg<SAR_MEAS_START1_SPEC>,
    pub sar_touch_ctrl1: Reg<SAR_TOUCH_CTRL1_SPEC>,
    pub sar_touch_thres1: Reg<SAR_TOUCH_THRES1_SPEC>,
    pub sar_touch_thres2: Reg<SAR_TOUCH_THRES2_SPEC>,
    pub sar_touch_thres3: Reg<SAR_TOUCH_THRES3_SPEC>,
    pub sar_touch_thres4: Reg<SAR_TOUCH_THRES4_SPEC>,
    pub sar_touch_thres5: Reg<SAR_TOUCH_THRES5_SPEC>,
    pub sar_touch_out1: Reg<SAR_TOUCH_OUT1_SPEC>,
    pub sar_touch_out2: Reg<SAR_TOUCH_OUT2_SPEC>,
    pub sar_touch_out3: Reg<SAR_TOUCH_OUT3_SPEC>,
    pub sar_touch_out4: Reg<SAR_TOUCH_OUT4_SPEC>,
    pub sar_touch_out5: Reg<SAR_TOUCH_OUT5_SPEC>,
    pub sar_touch_ctrl2: Reg<SAR_TOUCH_CTRL2_SPEC>,
    pub sar_touch_enable: Reg<SAR_TOUCH_ENABLE_SPEC>,
    pub sar_read_ctrl2: Reg<SAR_READ_CTRL2_SPEC>,
    pub sar_meas_start2: Reg<SAR_MEAS_START2_SPEC>,
    pub sar_dac_ctrl1: Reg<SAR_DAC_CTRL1_SPEC>,
    pub sar_dac_ctrl2: Reg<SAR_DAC_CTRL2_SPEC>,
    pub sar_meas_ctrl2: Reg<SAR_MEAS_CTRL2_SPEC>,
    pub sar_nouse: Reg<SAR_NOUSE_SPEC>,
    pub sardate: Reg<SARDATE_SPEC>,
    // some fields omitted
}

Register block

Fields

sar_read_ctrl: Reg<SAR_READ_CTRL_SPEC>

0x00 - SENS_SAR_READ_CTRL

sar_read_status1: Reg<SAR_READ_STATUS1_SPEC>

0x04 - SENS_SAR_READ_STATUS1

sar_meas_wait1: Reg<SAR_MEAS_WAIT1_SPEC>

0x08 - SENS_SAR_MEAS_WAIT1

sar_meas_wait2: Reg<SAR_MEAS_WAIT2_SPEC>

0x0c - SENS_SAR_MEAS_WAIT2

sar_meas_ctrl: Reg<SAR_MEAS_CTRL_SPEC>

0x10 - SENS_SAR_MEAS_CTRL

sar_read_status2: Reg<SAR_READ_STATUS2_SPEC>

0x14 - SENS_SAR_READ_STATUS2

ulp_cp_sleep_cyc0: Reg<ULP_CP_SLEEP_CYC0_SPEC>

0x18 - SENS_ULP_CP_SLEEP_CYC0

ulp_cp_sleep_cyc1: Reg<ULP_CP_SLEEP_CYC1_SPEC>

0x1c - SENS_ULP_CP_SLEEP_CYC1

ulp_cp_sleep_cyc2: Reg<ULP_CP_SLEEP_CYC2_SPEC>

0x20 - SENS_ULP_CP_SLEEP_CYC2

ulp_cp_sleep_cyc3: Reg<ULP_CP_SLEEP_CYC3_SPEC>

0x24 - SENS_ULP_CP_SLEEP_CYC3

ulp_cp_sleep_cyc4: Reg<ULP_CP_SLEEP_CYC4_SPEC>

0x28 - SENS_ULP_CP_SLEEP_CYC4

sar_start_force: Reg<SAR_START_FORCE_SPEC>

0x2c - SENS_SAR_START_FORCE

sar_mem_wr_ctrl: Reg<SAR_MEM_WR_CTRL_SPEC>

0x30 - SENS_SAR_MEM_WR_CTRL

sar_atten1: Reg<SAR_ATTEN1_SPEC>

0x34 - SENS_SAR_ATTEN1

sar_atten2: Reg<SAR_ATTEN2_SPEC>

0x38 - SENS_SAR_ATTEN2

sar_slave_addr1: Reg<SAR_SLAVE_ADDR1_SPEC>

0x3c - SENS_SAR_SLAVE_ADDR1

sar_slave_addr2: Reg<SAR_SLAVE_ADDR2_SPEC>

0x40 - SENS_SAR_SLAVE_ADDR2

sar_slave_addr3: Reg<SAR_SLAVE_ADDR3_SPEC>

0x44 - SENS_SAR_SLAVE_ADDR3

sar_slave_addr4: Reg<SAR_SLAVE_ADDR4_SPEC>

0x48 - SENS_SAR_SLAVE_ADDR4

sar_tsens_ctrl: Reg<SAR_TSENS_CTRL_SPEC>

0x4c - SENS_SAR_TSENS_CTRL

sar_i2c_ctrl: Reg<SAR_I2C_CTRL_SPEC>

0x50 - SENS_SAR_I2C_CTRL

sar_meas_start1: Reg<SAR_MEAS_START1_SPEC>

0x54 - SENS_SAR_MEAS_START1

sar_touch_ctrl1: Reg<SAR_TOUCH_CTRL1_SPEC>

0x58 - SENS_SAR_TOUCH_CTRL1

sar_touch_thres1: Reg<SAR_TOUCH_THRES1_SPEC>

0x5c - SENS_SAR_TOUCH_THRES1

sar_touch_thres2: Reg<SAR_TOUCH_THRES2_SPEC>

0x60 - SENS_SAR_TOUCH_THRES2

sar_touch_thres3: Reg<SAR_TOUCH_THRES3_SPEC>

0x64 - SENS_SAR_TOUCH_THRES3

sar_touch_thres4: Reg<SAR_TOUCH_THRES4_SPEC>

0x68 - SENS_SAR_TOUCH_THRES4

sar_touch_thres5: Reg<SAR_TOUCH_THRES5_SPEC>

0x6c - SENS_SAR_TOUCH_THRES5

sar_touch_out1: Reg<SAR_TOUCH_OUT1_SPEC>

0x70 - SENS_SAR_TOUCH_OUT1

sar_touch_out2: Reg<SAR_TOUCH_OUT2_SPEC>

0x74 - SENS_SAR_TOUCH_OUT2

sar_touch_out3: Reg<SAR_TOUCH_OUT3_SPEC>

0x78 - SENS_SAR_TOUCH_OUT3

sar_touch_out4: Reg<SAR_TOUCH_OUT4_SPEC>

0x7c - SENS_SAR_TOUCH_OUT4

sar_touch_out5: Reg<SAR_TOUCH_OUT5_SPEC>

0x80 - SENS_SAR_TOUCH_OUT5

sar_touch_ctrl2: Reg<SAR_TOUCH_CTRL2_SPEC>

0x84 - SENS_SAR_TOUCH_CTRL2

sar_touch_enable: Reg<SAR_TOUCH_ENABLE_SPEC>

0x8c - SENS_SAR_TOUCH_ENABLE

sar_read_ctrl2: Reg<SAR_READ_CTRL2_SPEC>

0x90 - SENS_SAR_READ_CTRL2

sar_meas_start2: Reg<SAR_MEAS_START2_SPEC>

0x94 - SENS_SAR_MEAS_START2

sar_dac_ctrl1: Reg<SAR_DAC_CTRL1_SPEC>

0x98 - SENS_SAR_DAC_CTRL1

sar_dac_ctrl2: Reg<SAR_DAC_CTRL2_SPEC>

0x9c - SENS_SAR_DAC_CTRL2

sar_meas_ctrl2: Reg<SAR_MEAS_CTRL2_SPEC>

0xa0 - SENS_SAR_MEAS_CTRL2

sar_nouse: Reg<SAR_NOUSE_SPEC>

0xf8 - SENS_SAR_NOUSE

sardate: Reg<SARDATE_SPEC>

0xfc - SENS_SARDATE

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