[][src]Struct esp32::rmt::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub ch0conf0: Reg<CH0CONF0_SPEC>,
    pub ch0conf1: Reg<CH0CONF1_SPEC>,
    pub ch1conf0: Reg<CH1CONF0_SPEC>,
    pub ch1conf1: Reg<CH1CONF1_SPEC>,
    pub ch2conf0: Reg<CH2CONF0_SPEC>,
    pub ch2conf1: Reg<CH2CONF1_SPEC>,
    pub ch3conf0: Reg<CH3CONF0_SPEC>,
    pub ch3conf1: Reg<CH3CONF1_SPEC>,
    pub ch4conf0: Reg<CH4CONF0_SPEC>,
    pub ch4conf1: Reg<CH4CONF1_SPEC>,
    pub ch5conf0: Reg<CH5CONF0_SPEC>,
    pub ch5conf1: Reg<CH5CONF1_SPEC>,
    pub ch6conf0: Reg<CH6CONF0_SPEC>,
    pub ch6conf1: Reg<CH6CONF1_SPEC>,
    pub ch7conf0: Reg<CH7CONF0_SPEC>,
    pub ch7conf1: Reg<CH7CONF1_SPEC>,
    pub ch0status: Reg<CH0STATUS_SPEC>,
    pub ch1status: Reg<CH1STATUS_SPEC>,
    pub ch2status: Reg<CH2STATUS_SPEC>,
    pub ch3status: Reg<CH3STATUS_SPEC>,
    pub ch4status: Reg<CH4STATUS_SPEC>,
    pub ch5status: Reg<CH5STATUS_SPEC>,
    pub ch6status: Reg<CH6STATUS_SPEC>,
    pub ch7status: Reg<CH7STATUS_SPEC>,
    pub ch0addr: Reg<CH0ADDR_SPEC>,
    pub ch1addr: Reg<CH1ADDR_SPEC>,
    pub ch2addr: Reg<CH2ADDR_SPEC>,
    pub ch3addr: Reg<CH3ADDR_SPEC>,
    pub ch4addr: Reg<CH4ADDR_SPEC>,
    pub ch5addr: Reg<CH5ADDR_SPEC>,
    pub ch6addr: Reg<CH6ADDR_SPEC>,
    pub ch7addr: Reg<CH7ADDR_SPEC>,
    pub int_raw: Reg<INT_RAW_SPEC>,
    pub int_st: Reg<INT_ST_SPEC>,
    pub int_ena: Reg<INT_ENA_SPEC>,
    pub int_clr: Reg<INT_CLR_SPEC>,
    pub ch0carrier_duty: Reg<CH0CARRIER_DUTY_SPEC>,
    pub ch1carrier_duty: Reg<CH1CARRIER_DUTY_SPEC>,
    pub ch2carrier_duty: Reg<CH2CARRIER_DUTY_SPEC>,
    pub ch3carrier_duty: Reg<CH3CARRIER_DUTY_SPEC>,
    pub ch4carrier_duty: Reg<CH4CARRIER_DUTY_SPEC>,
    pub ch5carrier_duty: Reg<CH5CARRIER_DUTY_SPEC>,
    pub ch6carrier_duty: Reg<CH6CARRIER_DUTY_SPEC>,
    pub ch7carrier_duty: Reg<CH7CARRIER_DUTY_SPEC>,
    pub ch0_tx_lim: Reg<CH0_TX_LIM_SPEC>,
    pub ch1_tx_lim: Reg<CH1_TX_LIM_SPEC>,
    pub ch2_tx_lim: Reg<CH2_TX_LIM_SPEC>,
    pub ch3_tx_lim: Reg<CH3_TX_LIM_SPEC>,
    pub ch4_tx_lim: Reg<CH4_TX_LIM_SPEC>,
    pub ch5_tx_lim: Reg<CH5_TX_LIM_SPEC>,
    pub ch6_tx_lim: Reg<CH6_TX_LIM_SPEC>,
    pub ch7_tx_lim: Reg<CH7_TX_LIM_SPEC>,
    pub apb_conf: Reg<APB_CONF_SPEC>,
    pub date: Reg<DATE_SPEC>,
    // some fields omitted
}

Register block

Fields

ch0conf0: Reg<CH0CONF0_SPEC>

0x20 - RMT_CH0CONF0

ch0conf1: Reg<CH0CONF1_SPEC>

0x24 - RMT_CH0CONF1

ch1conf0: Reg<CH1CONF0_SPEC>

0x28 - RMT_CH1CONF0

ch1conf1: Reg<CH1CONF1_SPEC>

0x2c - RMT_CH1CONF1

ch2conf0: Reg<CH2CONF0_SPEC>

0x30 - RMT_CH2CONF0

ch2conf1: Reg<CH2CONF1_SPEC>

0x34 - RMT_CH2CONF1

ch3conf0: Reg<CH3CONF0_SPEC>

0x38 - RMT_CH3CONF0

ch3conf1: Reg<CH3CONF1_SPEC>

0x3c - RMT_CH3CONF1

ch4conf0: Reg<CH4CONF0_SPEC>

0x40 - RMT_CH4CONF0

ch4conf1: Reg<CH4CONF1_SPEC>

0x44 - RMT_CH4CONF1

ch5conf0: Reg<CH5CONF0_SPEC>

0x48 - RMT_CH5CONF0

ch5conf1: Reg<CH5CONF1_SPEC>

0x4c - RMT_CH5CONF1

ch6conf0: Reg<CH6CONF0_SPEC>

0x50 - RMT_CH6CONF0

ch6conf1: Reg<CH6CONF1_SPEC>

0x54 - RMT_CH6CONF1

ch7conf0: Reg<CH7CONF0_SPEC>

0x58 - RMT_CH7CONF0

ch7conf1: Reg<CH7CONF1_SPEC>

0x5c - RMT_CH7CONF1

ch0status: Reg<CH0STATUS_SPEC>

0x60 - RMT_CH0STATUS

ch1status: Reg<CH1STATUS_SPEC>

0x64 - RMT_CH1STATUS

ch2status: Reg<CH2STATUS_SPEC>

0x68 - RMT_CH2STATUS

ch3status: Reg<CH3STATUS_SPEC>

0x6c - RMT_CH3STATUS

ch4status: Reg<CH4STATUS_SPEC>

0x70 - RMT_CH4STATUS

ch5status: Reg<CH5STATUS_SPEC>

0x74 - RMT_CH5STATUS

ch6status: Reg<CH6STATUS_SPEC>

0x78 - RMT_CH6STATUS

ch7status: Reg<CH7STATUS_SPEC>

0x7c - RMT_CH7STATUS

ch0addr: Reg<CH0ADDR_SPEC>

0x80 - RMT_CH0ADDR

ch1addr: Reg<CH1ADDR_SPEC>

0x84 - RMT_CH1ADDR

ch2addr: Reg<CH2ADDR_SPEC>

0x88 - RMT_CH2ADDR

ch3addr: Reg<CH3ADDR_SPEC>

0x8c - RMT_CH3ADDR

ch4addr: Reg<CH4ADDR_SPEC>

0x90 - RMT_CH4ADDR

ch5addr: Reg<CH5ADDR_SPEC>

0x94 - RMT_CH5ADDR

ch6addr: Reg<CH6ADDR_SPEC>

0x98 - RMT_CH6ADDR

ch7addr: Reg<CH7ADDR_SPEC>

0x9c - RMT_CH7ADDR

int_raw: Reg<INT_RAW_SPEC>

0xa0 - RMT_INT_RAW

int_st: Reg<INT_ST_SPEC>

0xa4 - RMT_INT_ST

int_ena: Reg<INT_ENA_SPEC>

0xa8 - RMT_INT_ENA

int_clr: Reg<INT_CLR_SPEC>

0xac - RMT_INT_CLR

ch0carrier_duty: Reg<CH0CARRIER_DUTY_SPEC>

0xb0 - RMT_CH0CARRIER_DUTY

ch1carrier_duty: Reg<CH1CARRIER_DUTY_SPEC>

0xb4 - RMT_CH1CARRIER_DUTY

ch2carrier_duty: Reg<CH2CARRIER_DUTY_SPEC>

0xb8 - RMT_CH2CARRIER_DUTY

ch3carrier_duty: Reg<CH3CARRIER_DUTY_SPEC>

0xbc - RMT_CH3CARRIER_DUTY

ch4carrier_duty: Reg<CH4CARRIER_DUTY_SPEC>

0xc0 - RMT_CH4CARRIER_DUTY

ch5carrier_duty: Reg<CH5CARRIER_DUTY_SPEC>

0xc4 - RMT_CH5CARRIER_DUTY

ch6carrier_duty: Reg<CH6CARRIER_DUTY_SPEC>

0xc8 - RMT_CH6CARRIER_DUTY

ch7carrier_duty: Reg<CH7CARRIER_DUTY_SPEC>

0xcc - RMT_CH7CARRIER_DUTY

ch0_tx_lim: Reg<CH0_TX_LIM_SPEC>

0xd0 - RMT_CH0_TX_LIM

ch1_tx_lim: Reg<CH1_TX_LIM_SPEC>

0xd4 - RMT_CH1_TX_LIM

ch2_tx_lim: Reg<CH2_TX_LIM_SPEC>

0xd8 - RMT_CH2_TX_LIM

ch3_tx_lim: Reg<CH3_TX_LIM_SPEC>

0xdc - RMT_CH3_TX_LIM

ch4_tx_lim: Reg<CH4_TX_LIM_SPEC>

0xe0 - RMT_CH4_TX_LIM

ch5_tx_lim: Reg<CH5_TX_LIM_SPEC>

0xe4 - RMT_CH5_TX_LIM

ch6_tx_lim: Reg<CH6_TX_LIM_SPEC>

0xe8 - RMT_CH6_TX_LIM

ch7_tx_lim: Reg<CH7_TX_LIM_SPEC>

0xec - RMT_CH7_TX_LIM

apb_conf: Reg<APB_CONF_SPEC>

0xf0 - RMT_APB_CONF

date: Reg<DATE_SPEC>

0xfc - RMT_DATE

Auto Trait Implementations

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
[src]

impl<T> Borrow<T> for T where
    T: ?Sized
[src]

impl<T> BorrowMut<T> for T where
    T: ?Sized
[src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.