[][src]Struct esp32::mcpwm::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub clk_cfg: Reg<CLK_CFG_SPEC>,
    pub timer0_cfg0: Reg<TIMER0_CFG0_SPEC>,
    pub timer0_cfg1: Reg<TIMER0_CFG1_SPEC>,
    pub timer0_sync: Reg<TIMER0_SYNC_SPEC>,
    pub timer0_status: Reg<TIMER0_STATUS_SPEC>,
    pub timer1_cfg0: Reg<TIMER1_CFG0_SPEC>,
    pub timer1_cfg1: Reg<TIMER1_CFG1_SPEC>,
    pub timer1_sync: Reg<TIMER1_SYNC_SPEC>,
    pub timer1_status: Reg<TIMER1_STATUS_SPEC>,
    pub timer2_cfg0: Reg<TIMER2_CFG0_SPEC>,
    pub timer2_cfg1: Reg<TIMER2_CFG1_SPEC>,
    pub timer2_sync: Reg<TIMER2_SYNC_SPEC>,
    pub timer2_status: Reg<TIMER2_STATUS_SPEC>,
    pub timer_synci_cfg: Reg<TIMER_SYNCI_CFG_SPEC>,
    pub operator_timersel: Reg<OPERATOR_TIMERSEL_SPEC>,
    pub gen0_stmp_cfg: Reg<GEN0_STMP_CFG_SPEC>,
    pub gen0_tstmp_a: Reg<GEN0_TSTMP_A_SPEC>,
    pub gen0_tstmp_b: Reg<GEN0_TSTMP_B_SPEC>,
    pub gen0_cfg0: Reg<GEN0_CFG0_SPEC>,
    pub gen0_force: Reg<GEN0_FORCE_SPEC>,
    pub gen0_a: Reg<GEN0_A_SPEC>,
    pub gen0_b: Reg<GEN0_B_SPEC>,
    pub dt0_cfg: Reg<DT0_CFG_SPEC>,
    pub dt0_fed_cfg: Reg<DT0_FED_CFG_SPEC>,
    pub dt0_red_cfg: Reg<DT0_RED_CFG_SPEC>,
    pub carrier0_cfg: Reg<CARRIER0_CFG_SPEC>,
    pub fh0_cfg0: Reg<FH0_CFG0_SPEC>,
    pub fh0_cfg1: Reg<FH0_CFG1_SPEC>,
    pub fh0_status: Reg<FH0_STATUS_SPEC>,
    pub gen1_stmp_cfg: Reg<GEN1_STMP_CFG_SPEC>,
    pub gen1_tstmp_a: Reg<GEN1_TSTMP_A_SPEC>,
    pub gen1_tstmp_b: Reg<GEN1_TSTMP_B_SPEC>,
    pub gen1_cfg0: Reg<GEN1_CFG0_SPEC>,
    pub gen1_force: Reg<GEN1_FORCE_SPEC>,
    pub gen1_a: Reg<GEN1_A_SPEC>,
    pub gen1_b: Reg<GEN1_B_SPEC>,
    pub dt1_cfg: Reg<DT1_CFG_SPEC>,
    pub dt1_fed_cfg: Reg<DT1_FED_CFG_SPEC>,
    pub dt1_red_cfg: Reg<DT1_RED_CFG_SPEC>,
    pub carrier1_cfg: Reg<CARRIER1_CFG_SPEC>,
    pub fh1_cfg0: Reg<FH1_CFG0_SPEC>,
    pub fh1_cfg1: Reg<FH1_CFG1_SPEC>,
    pub fh1_status: Reg<FH1_STATUS_SPEC>,
    pub gen2_stmp_cfg: Reg<GEN2_STMP_CFG_SPEC>,
    pub gen2_tstmp_a: Reg<GEN2_TSTMP_A_SPEC>,
    pub gen2_tstmp_b: Reg<GEN2_TSTMP_B_SPEC>,
    pub gen2_cfg0: Reg<GEN2_CFG0_SPEC>,
    pub gen2_force: Reg<GEN2_FORCE_SPEC>,
    pub gen2_a: Reg<GEN2_A_SPEC>,
    pub gen2_b: Reg<GEN2_B_SPEC>,
    pub dt2_cfg: Reg<DT2_CFG_SPEC>,
    pub dt2_fed_cfg: Reg<DT2_FED_CFG_SPEC>,
    pub dt2_red_cfg: Reg<DT2_RED_CFG_SPEC>,
    pub carrier2_cfg: Reg<CARRIER2_CFG_SPEC>,
    pub fh2_cfg0: Reg<FH2_CFG0_SPEC>,
    pub fh2_cfg1: Reg<FH2_CFG1_SPEC>,
    pub fh2_status: Reg<FH2_STATUS_SPEC>,
    pub fault_detect: Reg<FAULT_DETECT_SPEC>,
    pub cap_timer_cfg: Reg<CAP_TIMER_CFG_SPEC>,
    pub cap_timer_phase: Reg<CAP_TIMER_PHASE_SPEC>,
    pub cap_ch0_cfg: Reg<CAP_CH0_CFG_SPEC>,
    pub cap_ch1_cfg: Reg<CAP_CH1_CFG_SPEC>,
    pub cap_ch2_cfg: Reg<CAP_CH2_CFG_SPEC>,
    pub cap_ch0: Reg<CAP_CH0_SPEC>,
    pub cap_ch1: Reg<CAP_CH1_SPEC>,
    pub cap_ch2: Reg<CAP_CH2_SPEC>,
    pub cap_status: Reg<CAP_STATUS_SPEC>,
    pub update_cfg: Reg<UPDATE_CFG_SPEC>,
    pub mcmcpwm_int_ena_mcpwm: Reg<MCMCPWM_INT_ENA_MCPWM_SPEC>,
    pub mcmcpwm_int_raw_mcpwm: Reg<MCMCPWM_INT_RAW_MCPWM_SPEC>,
    pub mcmcpwm_int_st_mcpwm: Reg<MCMCPWM_INT_ST_MCPWM_SPEC>,
    pub mcmcpwm_int_clr_mcpwm: Reg<MCMCPWM_INT_CLR_MCPWM_SPEC>,
    pub clk: Reg<CLK_SPEC>,
    pub version: Reg<VERSION_SPEC>,
}

Register block

Fields

clk_cfg: Reg<CLK_CFG_SPEC>

0x00 - MCPWM_CLK_CFG

timer0_cfg0: Reg<TIMER0_CFG0_SPEC>

0x04 - MCPWM_TIMER0_CFG0

timer0_cfg1: Reg<TIMER0_CFG1_SPEC>

0x08 - MCPWM_TIMER0_CFG1

timer0_sync: Reg<TIMER0_SYNC_SPEC>

0x0c - MCPWM_TIMER0_SYNC

timer0_status: Reg<TIMER0_STATUS_SPEC>

0x10 - MCPWM_TIMER0_STATUS

timer1_cfg0: Reg<TIMER1_CFG0_SPEC>

0x14 - MCPWM_TIMER1_CFG0

timer1_cfg1: Reg<TIMER1_CFG1_SPEC>

0x18 - MCPWM_TIMER1_CFG1

timer1_sync: Reg<TIMER1_SYNC_SPEC>

0x1c - MCPWM_TIMER1_SYNC

timer1_status: Reg<TIMER1_STATUS_SPEC>

0x20 - MCPWM_TIMER1_STATUS

timer2_cfg0: Reg<TIMER2_CFG0_SPEC>

0x24 - MCPWM_TIMER2_CFG0

timer2_cfg1: Reg<TIMER2_CFG1_SPEC>

0x28 - MCPWM_TIMER2_CFG1

timer2_sync: Reg<TIMER2_SYNC_SPEC>

0x2c - MCPWM_TIMER2_SYNC

timer2_status: Reg<TIMER2_STATUS_SPEC>

0x30 - MCPWM_TIMER2_STATUS

timer_synci_cfg: Reg<TIMER_SYNCI_CFG_SPEC>

0x34 - MCPWM_TIMER_SYNCI_CFG

operator_timersel: Reg<OPERATOR_TIMERSEL_SPEC>

0x38 - MCPWM_OPERATOR_TIMERSEL

gen0_stmp_cfg: Reg<GEN0_STMP_CFG_SPEC>

0x3c - MCPWM_GEN0_STMP_CFG

gen0_tstmp_a: Reg<GEN0_TSTMP_A_SPEC>

0x40 - MCPWM_GEN0_TSTMP_A

gen0_tstmp_b: Reg<GEN0_TSTMP_B_SPEC>

0x44 - MCPWM_GEN0_TSTMP_B

gen0_cfg0: Reg<GEN0_CFG0_SPEC>

0x48 - MCPWM_GEN0_CFG0

gen0_force: Reg<GEN0_FORCE_SPEC>

0x4c - MCPWM_GEN0_FORCE

gen0_a: Reg<GEN0_A_SPEC>

0x50 - MCPWM_GEN0_A

gen0_b: Reg<GEN0_B_SPEC>

0x54 - MCPWM_GEN0_B

dt0_cfg: Reg<DT0_CFG_SPEC>

0x58 - MCPWM_DT0_CFG

dt0_fed_cfg: Reg<DT0_FED_CFG_SPEC>

0x5c - MCPWM_DT0_FED_CFG

dt0_red_cfg: Reg<DT0_RED_CFG_SPEC>

0x60 - MCPWM_DT0_RED_CFG

carrier0_cfg: Reg<CARRIER0_CFG_SPEC>

0x64 - MCPWM_CARRIER0_CFG

fh0_cfg0: Reg<FH0_CFG0_SPEC>

0x68 - MCPWM_FH0_CFG0

fh0_cfg1: Reg<FH0_CFG1_SPEC>

0x6c - MCPWM_FH0_CFG1

fh0_status: Reg<FH0_STATUS_SPEC>

0x70 - MCPWM_FH0_STATUS

gen1_stmp_cfg: Reg<GEN1_STMP_CFG_SPEC>

0x74 - MCPWM_GEN1_STMP_CFG

gen1_tstmp_a: Reg<GEN1_TSTMP_A_SPEC>

0x78 - MCPWM_GEN1_TSTMP_A

gen1_tstmp_b: Reg<GEN1_TSTMP_B_SPEC>

0x7c - MCPWM_GEN1_TSTMP_B

gen1_cfg0: Reg<GEN1_CFG0_SPEC>

0x80 - MCPWM_GEN1_CFG0

gen1_force: Reg<GEN1_FORCE_SPEC>

0x84 - MCPWM_GEN1_FORCE

gen1_a: Reg<GEN1_A_SPEC>

0x88 - MCPWM_GEN1_A

gen1_b: Reg<GEN1_B_SPEC>

0x8c - MCPWM_GEN1_B

dt1_cfg: Reg<DT1_CFG_SPEC>

0x90 - MCPWM_DT1_CFG

dt1_fed_cfg: Reg<DT1_FED_CFG_SPEC>

0x94 - MCPWM_DT1_FED_CFG

dt1_red_cfg: Reg<DT1_RED_CFG_SPEC>

0x98 - MCPWM_DT1_RED_CFG

carrier1_cfg: Reg<CARRIER1_CFG_SPEC>

0x9c - MCPWM_CARRIER1_CFG

fh1_cfg0: Reg<FH1_CFG0_SPEC>

0xa0 - MCPWM_FH1_CFG0

fh1_cfg1: Reg<FH1_CFG1_SPEC>

0xa4 - MCPWM_FH1_CFG1

fh1_status: Reg<FH1_STATUS_SPEC>

0xa8 - MCPWM_FH1_STATUS

gen2_stmp_cfg: Reg<GEN2_STMP_CFG_SPEC>

0xac - MCPWM_GEN2_STMP_CFG

gen2_tstmp_a: Reg<GEN2_TSTMP_A_SPEC>

0xb0 - MCPWM_GEN2_TSTMP_A

gen2_tstmp_b: Reg<GEN2_TSTMP_B_SPEC>

0xb4 - MCPWM_GEN2_TSTMP_B

gen2_cfg0: Reg<GEN2_CFG0_SPEC>

0xb8 - MCPWM_GEN2_CFG0

gen2_force: Reg<GEN2_FORCE_SPEC>

0xbc - MCPWM_GEN2_FORCE

gen2_a: Reg<GEN2_A_SPEC>

0xc0 - MCPWM_GEN2_A

gen2_b: Reg<GEN2_B_SPEC>

0xc4 - MCPWM_GEN2_B

dt2_cfg: Reg<DT2_CFG_SPEC>

0xc8 - MCPWM_DT2_CFG

dt2_fed_cfg: Reg<DT2_FED_CFG_SPEC>

0xcc - MCPWM_DT2_FED_CFG

dt2_red_cfg: Reg<DT2_RED_CFG_SPEC>

0xd0 - MCPWM_DT2_RED_CFG

carrier2_cfg: Reg<CARRIER2_CFG_SPEC>

0xd4 - MCPWM_CARRIER2_CFG

fh2_cfg0: Reg<FH2_CFG0_SPEC>

0xd8 - MCPWM_FH2_CFG0

fh2_cfg1: Reg<FH2_CFG1_SPEC>

0xdc - MCPWM_FH2_CFG1

fh2_status: Reg<FH2_STATUS_SPEC>

0xe0 - MCPWM_FH2_STATUS

fault_detect: Reg<FAULT_DETECT_SPEC>

0xe4 - MCPWM_FAULT_DETECT

cap_timer_cfg: Reg<CAP_TIMER_CFG_SPEC>

0xe8 - MCPWM_CAP_TIMER_CFG

cap_timer_phase: Reg<CAP_TIMER_PHASE_SPEC>

0xec - MCPWM_CAP_TIMER_PHASE

cap_ch0_cfg: Reg<CAP_CH0_CFG_SPEC>

0xf0 - MCPWM_CAP_CH0_CFG

cap_ch1_cfg: Reg<CAP_CH1_CFG_SPEC>

0xf4 - MCPWM_CAP_CH1_CFG

cap_ch2_cfg: Reg<CAP_CH2_CFG_SPEC>

0xf8 - MCPWM_CAP_CH2_CFG

cap_ch0: Reg<CAP_CH0_SPEC>

0xfc - MCPWM_CAP_CH0

cap_ch1: Reg<CAP_CH1_SPEC>

0x100 - MCPWM_CAP_CH1

cap_ch2: Reg<CAP_CH2_SPEC>

0x104 - MCPWM_CAP_CH2

cap_status: Reg<CAP_STATUS_SPEC>

0x108 - MCPWM_CAP_STATUS

update_cfg: Reg<UPDATE_CFG_SPEC>

0x10c - MCPWM_UPDATE_CFG

mcmcpwm_int_ena_mcpwm: Reg<MCMCPWM_INT_ENA_MCPWM_SPEC>

0x110 - MCMCPWM_INT_ENA_MCPWM

mcmcpwm_int_raw_mcpwm: Reg<MCMCPWM_INT_RAW_MCPWM_SPEC>

0x114 - MCMCPWM_INT_RAW_MCPWM

mcmcpwm_int_st_mcpwm: Reg<MCMCPWM_INT_ST_MCPWM_SPEC>

0x118 - MCMCPWM_INT_ST_MCPWM

mcmcpwm_int_clr_mcpwm: Reg<MCMCPWM_INT_CLR_MCPWM_SPEC>

0x11c - MCMCPWM_INT_CLR_MCPWM

clk: Reg<CLK_SPEC>

0x120 - MCPWM_CLK

version: Reg<VERSION_SPEC>

0x124 - MCPWM_VERSION

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